Annotation of sys/arch/sgi/pci/macepcibrvar.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: macepcibrvar.h,v 1.3 2004/10/20 12:49:15 pefo Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se)
! 5: *
! 6: * Redistribution and use in source and binary forms, with or without
! 7: * modification, are permitted provided that the following conditions
! 8: * are met:
! 9: * 1. Redistributions of source code must retain the above copyright
! 10: * notice, this list of conditions and the following disclaimer.
! 11: * 2. Redistributions in binary form must reproduce the above copyright
! 12: * notice, this list of conditions and the following disclaimer in the
! 13: * documentation and/or other materials provided with the distribution.
! 14: *
! 15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
! 16: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 17: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 18: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
! 19: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 20: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 21: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 22: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 23: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 24: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 25: * SUCH DAMAGE.
! 26: *
! 27: */
! 28:
! 29: #ifndef _PCIBRVAR_H_
! 30: #define _PCIBRVAR_H_
! 31:
! 32: #define MACE_PCI_IO_BASE 0x18000000
! 33: #define MACE_PCI_IO_SIZE 0x02000000
! 34: #define MACE_PCI_MEM_BASE 0x1a000000
! 35: #define MACE_PCI_MEM_SIZE 0x02000000
! 36:
! 37: struct mace_pcibr_softc {
! 38: struct device sc_dev;
! 39: struct mips_bus_space *sc_mem_bus_space;
! 40: struct mips_bus_space *sc_io_bus_space;
! 41: struct mips_pci_chipset sc_pc;
! 42: bus_space_tag_t sc_memt;
! 43: bus_space_handle_t sc_memh;
! 44: };
! 45:
! 46: u_int8_t mace_pcib_read_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
! 47: u_int16_t mace_pcib_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
! 48: u_int32_t mace_pcib_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
! 49: u_int64_t mace_pcib_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
! 50:
! 51: void mace_pcib_write_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
! 52: u_int8_t);
! 53: void mace_pcib_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
! 54: u_int16_t);
! 55: void mace_pcib_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
! 56: u_int32_t);
! 57: void mace_pcib_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
! 58: u_int64_t);
! 59:
! 60: int mace_pcib_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
! 61: bus_space_handle_t *);
! 62: void mace_pcib_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
! 63: int mace_pcib_space_region(bus_space_tag_t, bus_space_handle_t, bus_size_t,
! 64: bus_size_t, bus_space_handle_t *);
! 65:
! 66: #endif
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