Annotation of sys/arch/sgi/localbus/macebus.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: macebus.h,v 1.7 2005/12/19 21:37:48 miod Exp $ */
2:
3: /*
4: * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com).
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: *
15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25: * SUCH DAMAGE.
26: *
27: */
28:
29: #ifndef _MACEBUS_H_
30: #define _MACEBUS_H_ 1
31:
32: #include <machine/bus.h>
33:
34: /*
35: * Physical address of MACEBUS.
36: */
37: #define MACEBUS_BASE 0x1f000000
38:
39: /*
40: * Offsets for various I/O sections on MACEBUS
41: */
42: #define MACE_PCI_OFFS 0x00080000
43: #define MACE_VIN1_OFFS 0x00100000
44: #define MACE_VIN2_OFFS 0x00180000
45: #define MACE_VOUT_OFFS 0x00200000
46: #define MACE_IO_OFFS 0x00300000
47: #define MACE_ISAX_OFFS 0x00380000
48: #define MACE_ISAX_SIZE 0x00020000
49:
50: /*
51: * PCI control registers (relative MACE_PCI_OFFS)
52: */
53: #define MACE_PCI_ERROR_ADDRESS 0x0000
54: #define MACE_PCI_ERROR_FLAGS 0x0004
55: #define MACE_PCI_CONTROL 0x0008
56: #define MACE_PCI_REVISION 0x000c
57: #define MACE_PCI_FLUSH 0x000c
58: #define MACE_PCI_CFGADDR 0x0cf8
59: #define MACE_PCI_CFGDATA 0x0cfc
60:
61: #define MACE_PCI_INTCTRL 0x000000ff /* Interrupt control mask */
62:
63: /* PCI_ERROR_FLAGS Bits */
64: #define PERR_MASTER_ABORT 0x80000000
65: #define PERR_TARGET_ABORT 0x40000000
66: #define PERR_DATA_PARITY_ERR 0x20000000
67: #define PERR_RETRY_ERR 0x10000000
68: #define PERR_ILLEGAL_CMD 0x08000000
69: #define PERR_SYSTEM_ERR 0x04000000
70: #define PERR_INTERRUPT_TEST 0x02000000
71: #define PERR_PARITY_ERR 0x01000000
72: #define PERR_OVERRUN 0x00800000
73: #define PERR_RSVD 0x00400000
74: #define PERR_MEMORY_ADDR 0x00200000
75: #define PERR_CONFIG_ADDR 0x00100000
76: #define PERR_MASTER_ABORT_ADDR_VALID 0x00080000
77: #define PERR_TARGET_ABORT_ADDR_VALID 0x00040000
78: #define PERR_DATA_PARITY_ADDR_VALID 0x00020000
79: #define PERR_RETRY_ADDR_VALID 0x00010000
80:
81:
82: /*
83: * MACE ISA definitions.
84: */
85: #define MACE_ISA_OFFS (MACE_IO_OFFS+0x00010000)
86:
87: #define MACE_ISA_RING_BASE 0x0000
88: #define MACE_ISA_RING_ALIGN 0x00010000
89: #define MACE_ISA_MISC_REG 0x0008 /* Various status and controls */
90: #define MACE_ISA_INT_STAT 0x0010
91: #define MACE_ISA_INT_MASK 0x0018
92:
93: /* MACE_ISA_MISC_REG definitions */
94: #define MACE_ISA_MISC_RLED_OFF 0x0010 /* Turns off RED LED */
95: #define MACE_ISA_MISC_GLED_OFF 0x0020 /* Turns off GREEN LED */
96:
97: /* MACE_ISA_INT_* definitions */
98: #define MACE_ISA_INT_AUDIO 0x000000ff /* Audio ints */
99: #define MACE_ISA_INT_AUDIO_SC 0x02
100: #define MACE_ISA_INT_AUDIO_DMA1 0x04
101: #define MACE_ISA_INT_AUDIO_DMA2 0x10
102: #define MACE_ISA_INT_AUDIO_DMA3 0x40
103: #define MACE_ISA_INT_RTC 0x00000100 /* RTC */
104: #define MACE_ISA_INT_KBD 0x00000200 /* Keyboard */
105: #define MACE_ISA_INT_KBD_POLL 0x00000400 /* Keyboard polled */
106: #define MACE_ISA_INT_MOUSE 0x00000800 /* Mouse */
107: #define MACE_ISA_INT_MOUSE_POLL 0x00001000 /* Mouse polled */
108: #define MACE_ISA_INT_TIMER 0x0000e000 /* Timer/counter compare */
109: #define MACE_ISA_INT_PARALLEL 0x000f0000 /* Parallel port */
110: #define MACE_ISA_INT_SERIAL_1 0x03f00000 /* Serial port 1 */
111: #define MACE_ISA_INT_SERIAL_2 0xfc000000 /* Serial port 2 */
112:
113:
114: /* ISA Peripherals */
115: #define MACE_ISA_EPP_OFFS (MACE_ISAX_OFFS+0x00000000)
116: #define MACE_ISA_ECP_OFFS (MACE_ISAX_OFFS+0x00008000)
117: #define MACE_ISA_SER1_OFFS (MACE_ISAX_OFFS+0x00010000)
118: #define MACE_ISA_SER2_OFFS (MACE_ISAX_OFFS+0x00018000)
119: #define MACE_ISA_RTC_OFFS (MACE_ISAX_OFFS+0x00020000)
120: #define MACE_ISA_GAME_OFFS (MACE_ISAX_OFFS+0x00030000)
121:
122:
123: extern bus_space_t macebus_tag;
124:
125: u_int8_t mace_read_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
126: u_int16_t mace_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
127: u_int32_t mace_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
128: u_int64_t mace_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
129:
130: void mace_write_1(bus_space_tag_t, bus_space_handle_t, bus_size_t, u_int8_t);
131: void mace_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t, u_int16_t);
132: void mace_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t, u_int32_t);
133: void mace_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t, u_int64_t);
134:
135: int mace_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, bus_space_handle_t *);
136: void mace_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
137: int mace_space_region(bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_size_t, bus_space_handle_t *);
138:
139: #endif /* _MACEBUS_H_ */
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