Annotation of sys/arch/sgi/dev/if_mecreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_mecreg.h,v 1.2 2007/07/31 19:10:22 deraadt Exp $ */
2: /* $NetBSD: if_mecreg.h,v 1.2 2004/07/11 03:13:04 tsutsui Exp $ */
3:
4: /*
5: * Copyright (c) 2001 Christopher Sekiya
6: * Copyright (c) 2000 Soren S. Jorvang
7: * All rights reserved.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. All advertising materials mentioning features or use of this software
18: * must display the following acknowledgement:
19: * This product includes software developed for the
20: * NetBSD Project. See http://www.NetBSD.org/ for
21: * information about NetBSD.
22: * 4. The name of the author may not be used to endorse or promote products
23: * derived from this software without specific prior written permission.
24: *
25: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35: */
36:
37: /*
38: * MACE MAC110 Ethernet register definitions
39: */
40:
41: #define MEC_MAC_CONTROL 0x00
42: #define MEC_MAC_CORE_RESET 0x0000000000000001 /* reset signal */
43: #define MEC_MAC_FULL_DUPLEX 0x0000000000000002 /* 1 to enable */
44: #define MEC_MAC_INT_LOOPBACK 0x0000000000000004 /* 0 = normal op */
45: #define MEC_MAC_SPEED_SELECT 0x0000000000000008 /* 0/1 10/100 */
46: #define MEC_MAC_MII_SELECT 0x0000000000000010 /* MII/SIA */
47: #define MEC_MAC_FILTER_MASK 0x0000000000000060
48: #define MEC_MAC_FILTER_STATION 0x0000000000000000
49: #define MEC_MAC_FILTER_MATCHMULTI 0x0000000000000020
50: #define MEC_MAC_FILTER_ALLMULTI 0x0000000000000040
51: #define MEC_MAC_FILTER_PROMISC 0x0000000000000060
52: #define MEC_MAC_LINK_FAILURE 0x0000000000000080
53: #define MEC_MAC_IPGT 0x0000000000007f00 /* interpacket gap */
54: #define MEC_MAC_IPGT_SHIFT 8
55: #define MEC_MAC_IPGR1 0x00000000003f8000
56: #define MEC_MAC_IPGR1_SHIFT 15
57: #define MEC_MAC_IPGR2 0x000000001fc00000
58: #define MEC_MAC_IPGR2_SHIFT 22
59: #define MEC_MAC_REVISION 0x00000000e0000000
60: #define MEC_MAC_REVISION_SHIFT 29
61:
62: #define MEC_MAC_IPG_DEFAULT \
63: (21 << MEC_MAC_IPGT_SHIFT) | \
64: (17 << MEC_MAC_IPGR1_SHIFT) | \
65: (11 << MEC_MAC_IPGR2_SHIFT)
66:
67: #define MEC_INT_STATUS 0x08
68: #define MEC_INT_STATUS_MASK 0x00000000000000ff
69: #define MEC_INT_TX_EMPTY 0x0000000000000001
70: #define MEC_INT_TX_PACKET_SENT 0x0000000000000002
71: #define MEC_INT_TX_LINK_FAIL 0x0000000000000004
72: #define MEC_INT_TX_MEM_ERROR 0x0000000000000008
73: #define MEC_INT_TX_ABORT 0x0000000000000010
74: #define MEC_INT_RX_THRESHOLD 0x0000000000000020
75: #define MEC_INT_RX_FIFO_UNDERFLOW 0x0000000000000040
76: #define MEC_INT_RX_DMA_UNDERFLOW 0x0000000000000080
77: #define MEC_INT_RX_MCL_FIFO_ALIAS 0x0000000000001f00
78: #define MEC_INT_TX_RING_BUFFER_ALIAS 0x0000000001ff0000
79: #define MEC_INT_RX_SEQUENCE_NUMBER 0x000000003e000000
80: #define MEC_INT_MCAST_HASH_OUTPUT 0x0000000040000000
81:
82: #define MEC_DMA_CONTROL 0x10
83: #define MEC_DMA_TX_INT_ENABLE 0x0000000000000001
84: #define MEC_DMA_TX_DMA_ENABLE 0x0000000000000002
85: #define MEC_DMA_TX_RING_SIZE_MASK 0x000000000000000c
86: #define MEC_DMA_RX_INT_THRESHOLD 0x00000000000001f0
87: #define MEC_DMA_RX_INT_THRESH_SHIFT 4
88: #define MEC_DMA_RX_INT_ENABLE 0x0000000000000200
89: #define MEC_DMA_RX_RUNT 0x0000000000000400
90: #define MEC_DMA_RX_PACKET_GATHER 0x0000000000000800
91: #define MEC_DMA_RX_DMA_OFFSET 0x0000000000007000
92: #define MEC_DMA_RX_DMA_OFFSET_SHIFT 12
93: #define MEC_DMA_RX_DMA_ENABLE 0x0000000000008000
94:
95: #define MEC_TIMER 0x18
96: #define MEC_TX_ALIAS 0x20
97: #define MEC_TX_ALIAS_INT_ENABLE 0x0000000000000001
98:
99: #define MEC_RX_ALIAS 0x28
100: #define MEC_RX_ALIAS_INT_ENABLE 0x0000000000000200
101: #define MEC_RX_ALIAS_INT_THRESHOLD 0x00000000000001f0
102:
103: #define MEC_TX_RING_PTR 0x30
104: #define MEC_TX_RING_WRITE_PTR 0x00000000000001ff
105: #define MEC_TX_RING_READ_PTR 0x0000000001ff0000
106: #define MEC_TX_RING_PTR_ALIAS 0x38
107:
108: #define MEC_RX_FIFO 0x40
109: #define MEC_RX_FIFO_ELEMENT_COUNT 0x000000000000001f
110: #define MEC_RX_FIFO_READ_PTR 0x0000000000000f00
111: #define MEC_RX_FIFO_GEN_NUMBER 0x0000000000001000
112: #define MEC_RX_FIFO_WRITE_PTR 0x00000000000f0000
113: #define MEC_RX_FIFO_GEN_NUMBER_2 0x0000000000100000
114:
115: #define MEC_RX_FIFO_ALIAS1 0x48
116: #define MEC_RX_FIFO_ALIAS2 0x50
117: #define MEC_TX_VECTOR 0x58
118: #define MEC_IRQ_VECTOR 0x58
119:
120: #define MEC_PHY_DATA_PAD 0x60 /* XXX ? */
121: #define MEC_PHY_DATA 0x64
122: #define MEC_PHY_DATA_BUSY 0x00010000
123: #define MEC_PHY_DATA_VALUE 0x0000ffff
124:
125: #define MEC_PHY_ADDRESS_PAD 0x68 /* XXX ? */
126: #define MEC_PHY_ADDRESS 0x6c
127: #define MEC_PHY_ADDR_REGISTER 0x0000001f
128: #define MEC_PHY_ADDR_DEVICE 0x000003e0
129: #define MEC_PHY_ADDR_DEVSHIFT 5
130:
131: #define MEC_PHY_READ_INITIATE 0x70
132: #define MEC_PHY_BACKOFF 0x78
133:
134: #define MEC_STATION 0xa0
135: #define MEC_STATION_ALT 0xa8
136: #define MEC_STATION_MASK 0x0000ffffffffffffULL
137:
138: #define MEC_MULTICAST 0xb0
139: #define MEC_TX_RING_BASE 0xb8
140: #define MEC_TX_PKT1_CMD_1 0xc0
141: #define MEC_TX_PKT1_BUFFER_1 0xc8
142: #define MEC_TX_PKT1_BUFFER_2 0xd0
143: #define MEC_TX_PKT1_BUFFER_3 0xd8
144: #define MEC_TX_PKT2_CMD_1 0xe0
145: #define MEC_TX_PKT2_BUFFER_1 0xe8
146: #define MEC_TX_PKT2_BUFFER_2 0xf0
147: #define MEC_TX_PKT2_BUFFER_3 0xf8
148:
149: #define MEC_MCL_RX_FIFO 0x100
150:
151: #define MEC_NREGS 0x200
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