Annotation of sys/arch/powerpc/powerpc/fpu.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: fpu.c,v 1.10 2007/03/20 20:59:53 kettenis Exp $ */
2: /* $NetBSD: fpu.c,v 1.1 1996/09/30 16:34:44 ws Exp $ */
3:
4: /*
5: * Copyright (C) 1996 Wolfgang Solfrank.
6: * Copyright (C) 1996 TooLs GmbH.
7: * All rights reserved.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. All advertising materials mentioning features or use of this software
18: * must display the following acknowledgement:
19: * This product includes software developed by TooLs GmbH.
20: * 4. The name of TooLs GmbH may not be used to endorse or promote products
21: * derived from this software without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26: * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27: * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29: * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33: */
34: #include <sys/param.h>
35: #include <sys/proc.h>
36: #include <sys/user.h>
37:
38: #include <machine/fpu.h>
39: #include <machine/psl.h>
40:
41: void
42: enable_fpu(struct proc *p)
43: {
44: struct cpu_info *ci = curcpu();
45: struct pcb *pcb = &p->p_addr->u_pcb;
46: struct trapframe *tf = trapframe(p);
47: int msr;
48:
49: if (!(pcb->pcb_flags & PCB_FPU)) {
50: bzero(&pcb->pcb_fpu, sizeof pcb->pcb_fpu);
51: pcb->pcb_flags |= PCB_FPU;
52: }
53: msr = ppc_mfmsr();
54: ppc_mtmsr((msr & ~PSL_EE) | PSL_FP);
55: __asm volatile("isync");
56:
57: asm volatile ("lfd 0,0(%0); mtfsf 0xff,0" :: "b"(&pcb->pcb_fpu.fpcsr));
58: asm ("lfd 0,0(%0);"
59: "lfd 1,8(%0);"
60: "lfd 2,16(%0);"
61: "lfd 3,24(%0);"
62: "lfd 4,32(%0);"
63: "lfd 5,40(%0);"
64: "lfd 6,48(%0);"
65: "lfd 7,56(%0);"
66: "lfd 8,64(%0);"
67: "lfd 9,72(%0);"
68: "lfd 10,80(%0);"
69: "lfd 11,88(%0);"
70: "lfd 12,96(%0);"
71: "lfd 13,104(%0);"
72: "lfd 14,112(%0);"
73: "lfd 15,120(%0);"
74: "lfd 16,128(%0);"
75: "lfd 17,136(%0);"
76: "lfd 18,144(%0);"
77: "lfd 19,152(%0);"
78: "lfd 20,160(%0);"
79: "lfd 21,168(%0);"
80: "lfd 22,176(%0);"
81: "lfd 23,184(%0);"
82: "lfd 24,192(%0);"
83: "lfd 25,200(%0);"
84: "lfd 26,208(%0);"
85: "lfd 27,216(%0);"
86: "lfd 28,224(%0);"
87: "lfd 29,232(%0);"
88: "lfd 30,240(%0);"
89: "lfd 31,248(%0)" :: "b"(&pcb->pcb_fpu.fpr[0]));
90: ci->ci_fpuproc = p;
91: tf->srr1 |= PSL_FP;
92: ppc_mtmsr(msr);
93: __asm volatile("isync");
94: }
95:
96: void
97: save_fpu()
98: {
99: struct cpu_info *ci = curcpu();
100: struct pcb *pcb;
101: struct proc *p;
102: struct trapframe *tf;
103: int msr;
104:
105: msr = ppc_mfmsr();
106: ppc_mtmsr((msr & ~PSL_EE) | PSL_FP);
107:
108: p = ci->ci_fpuproc;
109:
110: if (p == NULL) {
111: ppc_mtmsr(msr);
112: return;
113: }
114:
115: pcb = &p->p_addr->u_pcb;
116:
117: __asm volatile("isync");
118:
119: asm ("stfd 0,0(%0);"
120: "stfd 1,8(%0);"
121: "stfd 2,16(%0);"
122: "stfd 3,24(%0);"
123: "stfd 4,32(%0);"
124: "stfd 5,40(%0);"
125: "stfd 6,48(%0);"
126: "stfd 7,56(%0);"
127: "stfd 8,64(%0);"
128: "stfd 9,72(%0);"
129: "stfd 10,80(%0);"
130: "stfd 11,88(%0);"
131: "stfd 12,96(%0);"
132: "stfd 13,104(%0);"
133: "stfd 14,112(%0);"
134: "stfd 15,120(%0);"
135: "stfd 16,128(%0);"
136: "stfd 17,136(%0);"
137: "stfd 18,144(%0);"
138: "stfd 19,152(%0);"
139: "stfd 20,160(%0);"
140: "stfd 21,168(%0);"
141: "stfd 22,176(%0);"
142: "stfd 23,184(%0);"
143: "stfd 24,192(%0);"
144: "stfd 25,200(%0);"
145: "stfd 26,208(%0);"
146: "stfd 27,216(%0);"
147: "stfd 28,224(%0);"
148: "stfd 29,232(%0);"
149: "stfd 30,240(%0);"
150: "stfd 31,248(%0)" :: "b"(&pcb->pcb_fpu.fpr[0]));
151: asm volatile ("mffs 0; stfd 0,0(%0)" :: "b"(&pcb->pcb_fpu.fpcsr));
152: asm ("lfd 0,0(%0);" :: "b"(&pcb->pcb_fpu.fpr[0]));
153:
154: tf = trapframe(ci->ci_fpuproc);
155: tf->srr1 &= ~PSL_FP;
156: ci->ci_fpuproc = NULL;
157:
158: ppc_mtmsr(msr);
159: __asm volatile("isync");
160: }
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