Annotation of sys/arch/mvmeppc/include/bus_mi.h, Revision 1.1.1.1
1.1 nbrk 1: /* $NetBSD: bus.h,v 1.1 2001/06/06 17:37:37 matt Exp $ */
2: /* $OpenBSD: bus_mi.h,v 1.8 2007/04/10 18:02:48 miod Exp $ */
3:
4: /*-
5: * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10: * NASA Ames Research Center.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the NetBSD
23: * Foundation, Inc. and its contributors.
24: * 4. Neither the name of The NetBSD Foundation nor the names of its
25: * contributors may be used to endorse or promote products derived
26: * from this software without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: /*
42: * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
43: * Copyright (c) 1996 Jason R. Thorpe. All rights reserved.
44: * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
45: *
46: * Redistribution and use in source and binary forms, with or without
47: * modification, are permitted provided that the following conditions
48: * are met:
49: * 1. Redistributions of source code must retain the above copyright
50: * notice, this list of conditions and the following disclaimer.
51: * 2. Redistributions in binary form must reproduce the above copyright
52: * notice, this list of conditions and the following disclaimer in the
53: * documentation and/or other materials provided with the distribution.
54: * 3. All advertising materials mentioning features or use of this software
55: * must display the following acknowledgement:
56: * This product includes software developed by Christopher G. Demetriou
57: * for the NetBSD Project.
58: * 4. The name of the author may not be used to endorse or promote products
59: * derived from this software without specific prior written permission
60: *
61: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
62: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
63: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
64: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
65: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
66: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
67: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
68: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
69: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
70: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
71: */
72:
73: /*
74: * Copyright (c) 1997 Per Fogelstrom. All rights reserved.
75: * Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
76: *
77: * Redistribution and use in source and binary forms, with or without
78: * modification, are permitted provided that the following conditions
79: * are met:
80: * 1. Redistributions of source code must retain the above copyright
81: * notice, this list of conditions and the following disclaimer.
82: * 2. Redistributions in binary form must reproduce the above copyright
83: * notice, this list of conditions and the following disclaimer in the
84: * documentation and/or other materials provided with the distribution.
85: * 3. All advertising materials mentioning features or use of this software
86: * must display the following acknowledgement:
87: * This product includes software developed by Christopher G. Demetriou
88: * for the NetBSD Project.
89: * 4. The name of the author may not be used to endorse or promote products
90: * derived from this software without specific prior written permission
91: *
92: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
93: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
94: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
95: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
96: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
97: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
98: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
99: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
100: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
101: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
102: */
103:
104: #ifndef _POWERPC_BUS_H_
105: #define _POWERPC_BUS_H_
106:
107: #include <machine/pio.h>
108:
109: /*
110: * Bus access types.
111: */
112: typedef u_int32_t bus_addr_t;
113: typedef u_int32_t bus_size_t;
114: typedef u_int32_t bus_space_handle_t;
115: typedef const struct ppc_bus_space *bus_space_tag_t;
116:
117: struct ppc_bus_space {
118: u_int32_t pbs_type;
119: bus_addr_t pbs_offset;
120: bus_addr_t pbs_base;
121: bus_addr_t pbs_limit;
122: int (*pbs_map)(bus_space_tag_t, bus_addr_t, bus_size_t, int,
123: bus_space_handle_t *);
124: void (*pbs_unmap)(bus_space_tag_t, bus_space_handle_t,
125: bus_size_t);
126: int (*pbs_alloc)(bus_space_tag_t, bus_addr_t, bus_addr_t,
127: bus_size_t, bus_size_t align, bus_size_t, int, bus_addr_t *,
128: bus_space_handle_t *);
129: void (*pbs_free)(bus_space_tag_t, bus_space_handle_t, bus_size_t);
130: };
131:
132: #define BUS_SPACE_MAP_CACHEABLE 0x01
133: #define BUS_SPACE_MAP_LINEAR 0x02
134: #define BUS_SPACE_MAP_PREFETCHABLE 0x04
135:
136: #ifdef __STDC__
137: #define CAT(a,b) a##b
138: #define CAT3(a,b,c) a##b##c
139: #else
140: #define CAT(a,b) a/**/b
141: #define CAT3(a,b,c) a/**/b/**/c
142: #endif
143:
144: /*
145: * Access methods for bus resources
146: */
147:
148: #define __BUS_SPACE_HAS_STREAM_METHODS
149:
150: /*
151: * int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
152: * bus_size_t size, int flags, bus_space_handle_t *bshp);
153: *
154: * Map a region of bus space.
155: */
156:
157: #define bus_space_map(t, a, s, f, hp) \
158: ((*(t)->pbs_map)((t), (a), (s), (f), (hp)))
159:
160: /*
161: * int bus_space_unmap(bus_space_tag_t t,
162: * bus_space_handle_t bsh, bus_size_t size);
163: *
164: * Unmap a region of bus space.
165: */
166:
167: #define bus_space_unmap(t, h, s) \
168: ((void)(*(t)->pbs_unmap)((t), (h), (s)))
169:
170: /*
171: * int bus_space_subregion(bus_space_tag_t t,
172: * bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
173: * bus_space_handle_t *nbshp);
174: *
175: * Get a new handle for a subregion of an already-mapped area of bus space.
176: */
177:
178: #define bus_space_subregion(t, h, o, s, hp) \
179: ((*(hp) = (h) + (o)), 0)
180:
181: /*
182: * int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
183: * bus_addr_t rend, bus_size_t size, bus_size_t align,
184: * bus_size_t boundary, int flags, bus_addr_t *bpap,
185: * bus_space_handle_t *bshp);
186: *
187: * Allocate a region of bus space.
188: */
189:
190: #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
191: ((*(t)->pbs_alloc)((t), (rs), (re), (s), (a), (b), (f), (ap), (hp)))
192:
193: /*
194: * int bus_space_free(bus_space_tag_t t,
195: * bus_space_handle_t bsh, bus_size_t size);
196: *
197: * Free a region of bus space.
198: */
199:
200: #define bus_space_free(t, h, s) \
201: ((void)(*(t)->pbs_free)((t), (h), (s)))
202:
203: /*
204: * u_intN_t bus_space_read_N(bus_space_tag_t tag,
205: * bus_space_handle_t bsh, bus_size_t offset);
206: *
207: * Read a 1, 2, 4, or 8 byte quantity from bus space
208: * described by tag/handle/offset.
209: */
210:
211: #define bus_space_read(n,m) \
212: static __inline CAT3(u_int,m,_t) \
213: CAT(bus_space_read_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \
214: bus_size_t offset) \
215: { \
216: return CAT3(in,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (offset))); \
217: }
218:
219: bus_space_read(1,8)
220: bus_space_read(2,16)
221: bus_space_read(4,32)
222: #define bus_space_read_8 !!! bus_space_read_8 unimplemented !!!
223:
224: /*
225: * u_intN_t bus_space_read_stream_N(bus_space_tag_t tag,
226: * bus_space_handle_t bsh, bus_size_t offset);
227: *
228: * Read a 2, 4, or 8 byte stream quantity from bus space
229: * described by tag/handle/offset.
230: */
231:
232: #define bus_space_read_stream(n,m) \
233: static __inline CAT3(u_int,m,_t) \
234: CAT(bus_space_read_stream_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \
235: bus_size_t offset) \
236: { \
237: return CAT(in,m)((volatile CAT3(u_int,m,_t) *)(bsh + (offset))); \
238: }
239:
240: bus_space_read_stream(2,16)
241: bus_space_read_stream(4,32)
242: #define bus_space_read_stream_8 !!! bus_space_read_stream_8 unimplemented !!!
243:
244: /*
245: * void bus_space_read_multi_N(bus_space_tag_t tag,
246: * bus_space_handle_t bsh, bus_size_t offset,
247: * u_intN_t *addr, size_t count);
248: *
249: * Read `count' 1, 2, 4, or 8 byte quantities from bus space
250: * described by tag/handle/offset and copy into buffer provided.
251: */
252:
253: #define bus_space_read_multi(n,m) \
254: static __inline void \
255: CAT(bus_space_read_multi_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \
256: bus_size_t offset, CAT3(u_int,m,_t) *addr, size_t count) \
257: { \
258: while (count--) \
259: *addr++ = CAT(bus_space_read_,n)(tag, bsh, offset); \
260: }
261:
262: bus_space_read_multi(1,8)
263: bus_space_read_multi(2,16)
264: bus_space_read_multi(4,32)
265: #define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!!
266:
267: #if 0
268: /*
269: * void bus_space_read_multi_stream_N(bus_space_tag_t tag,
270: * bus_space_handle_t bsh, bus_size_t offset,
271: * u_intN_t *addr, size_t count);
272: *
273: * Read `count' 2, 4, or 8 byte stream quantities from bus space
274: * described by tag/handle/offset and copy into buffer provided.
275: */
276:
277: #define bus_space_read_multi_stream(n,m) \
278: static __inline void \
279: CAT(bus_space_read_multi_stream_,n)(bus_space_tag_t tag, \
280: bus_space_handle_t bsh, \
281: bus_size_t offset, CAT3(u_int,m,_t) *addr, size_t count) \
282: { \
283: CAT(ins,m)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), \
284: (CAT3(u_int,m,_t) *)addr, (size_t)count); \
285: }
286:
287: bus_space_read_multi_stream(2,16)
288: bus_space_read_multi_stream(4,32)
289: #define bus_space_read_multi_stream_8 \
290: !!! bus_space_read_multi_stream_8 not implemented !!!
291:
292: /*
293: * void bus_space_write_N(bus_space_tag_t tag,
294: * bus_space_handle_t bsh, bus_size_t offset,
295: * u_intN_t value);
296: *
297: * Write the 1, 2, 4, or 8 byte value `value' to bus space
298: * described by tag/handle/offset.
299: */
300: #endif
301:
302: #define bus_space_write(n,m) \
303: static __inline void \
304: CAT(bus_space_write_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \
305: bus_size_t offset, CAT3(u_int,m,_t) x) \
306: { \
307: CAT3(out,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), x); \
308: }
309:
310: bus_space_write(1,8)
311: bus_space_write(2,16)
312: bus_space_write(4,32)
313: #define bus_space_write_8 !!! bus_space_write_8 unimplemented !!!
314:
315: /*
316: * void bus_space_write_stream_N(bus_space_tag_t tag,
317: * bus_space_handle_t bsh, bus_size_t offset,
318: * u_intN_t value);
319: *
320: * Write the 2, 4, or 8 byte stream value `value' to bus space
321: * described by tag/handle/offset.
322: */
323:
324: #define bus_space_write_stream(n,m) \
325: static __inline void \
326: CAT(bus_space_write_stream_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \
327: bus_size_t offset, CAT3(u_int,m,_t) x) \
328: { \
329: CAT(out,m)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), x); \
330: }
331:
332: bus_space_write_stream(2,16)
333: bus_space_write_stream(4,32)
334: #define bus_space_write_stream_8 !!! bus_space_write_stream_8 unimplemented !!!
335:
336: /*
337: * void bus_space_write_multi_N(bus_space_tag_t tag,
338: * bus_space_handle_t bsh, bus_size_t offset,
339: * const u_intN_t *addr, size_t count);
340: *
341: * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
342: * provided to bus space described by tag/handle/offset.
343: */
344:
345: #define bus_space_write_multi(n,m) \
346: static __inline void \
347: CAT(bus_space_write_multi_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \
348: bus_size_t offset, const CAT3(u_int,m,_t) *addr, size_t count) \
349: { \
350: while (count--) \
351: CAT(bus_space_write_,n)(tag, bsh, offset, *addr++); \
352: }
353:
354: bus_space_write_multi(1,8)
355: bus_space_write_multi(2,16)
356: bus_space_write_multi(4,32)
357: #define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
358:
359: #if 0
360: /*
361: * void bus_space_write_multi_stream_N(bus_space_tag_t tag,
362: * bus_space_handle_t bsh, bus_size_t offset,
363: * const u_intN_t *addr, size_t count);
364: *
365: * Write `count' 2, 4, or 8 byte stream quantities from the buffer
366: * provided to bus space described by tag/handle/offset.
367: */
368:
369: #define bus_space_write_multi_stream(n,m) \
370: static __inline void \
371: CAT(bus_space_write_multi_stream_,n)(bus_space_tag_t tag, \
372: bus_space_handle_t bsh, \
373: bus_size_t offset, const CAT3(u_int,m,_t) *addr, size_t count) \
374: { \
375: CAT(outs,m)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), \
376: (CAT3(u_int,m,_t) *)addr, (size_t)count); \
377: }
378:
379: bus_space_write_multi_stream(2,16)
380: bus_space_write_multi_stream(4,32)
381: #define bus_space_write_multi_stream_8 \
382: !!! bus_space_write_multi_stream_8 not implemented !!!
383: #endif
384:
385: /*
386: * void bus_space_read_region_N(bus_space_tag_t tag,
387: * bus_space_handle_t bsh, bus_size_t offset,
388: * u_intN_t *addr, size_t count);
389: *
390: * Read `count' 1, 2, 4, or 8 byte quantities from bus space
391: * described by tag/handle and starting at `offset' and copy into
392: * buffer provided.
393: */
394: static __inline void bus_space_read_region_1(bus_space_tag_t,
395: bus_space_handle_t, bus_size_t, u_int8_t *, size_t);
396: static __inline void bus_space_read_region_2(bus_space_tag_t,
397: bus_space_handle_t, bus_size_t, u_int16_t *, size_t);
398: static __inline void bus_space_read_region_4(bus_space_tag_t,
399: bus_space_handle_t, bus_size_t, u_int32_t *, size_t);
400:
401: static __inline void
402: bus_space_read_region_1(tag, bsh, offset, addr, count)
403: bus_space_tag_t tag;
404: bus_space_handle_t bsh;
405: bus_size_t offset;
406: u_int8_t *addr;
407: size_t count;
408: {
409: volatile u_int8_t *s;
410:
411: s = (volatile u_int8_t *)(bsh + offset);
412: while (count--)
413: *addr++ = *s++;
414: __asm__ volatile("eieio; sync");
415: }
416:
417: static __inline void
418: bus_space_read_region_2(tag, bsh, offset, addr, count)
419: bus_space_tag_t tag;
420: bus_space_handle_t bsh;
421: bus_size_t offset;
422: u_int16_t *addr;
423: size_t count;
424: {
425: volatile u_int16_t *s;
426:
427: s = (volatile u_int16_t *)(bsh + offset);
428: while (count--)
429: __asm__ volatile("lhbrx %0, 0, %1" :
430: "=r"(*addr++) : "r"(s++));
431: __asm__ volatile("eieio; sync");
432: }
433:
434: static __inline void
435: bus_space_read_region_4(tag, bsh, offset, addr, count)
436: bus_space_tag_t tag;
437: bus_space_handle_t bsh;
438: bus_size_t offset;
439: u_int32_t *addr;
440: size_t count;
441: {
442: volatile u_int32_t *s;
443:
444: s = (volatile u_int32_t *)(bsh + offset);
445: while (count--)
446: __asm__ volatile("lwbrx %0, 0, %1" :
447: "=r"(*addr++) : "r"(s++));
448: __asm__ volatile("eieio; sync");
449: }
450:
451: #define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!!
452:
453: /*
454: * void bus_space_read_region_stream_N(bus_space_tag_t tag,
455: * bus_space_handle_t bsh, bus_size_t offset,
456: * u_intN_t *addr, size_t count);
457: *
458: * Read `count' 2, 4, or 8 byte stream quantities from bus space
459: * described by tag/handle and starting at `offset' and copy into
460: * buffer provided.
461: */
462: static __inline void bus_space_read_region_stream_2(bus_space_tag_t,
463: bus_space_handle_t, bus_size_t, u_int16_t *, size_t);
464: static __inline void bus_space_read_region_stream_4(bus_space_tag_t,
465: bus_space_handle_t, bus_size_t, u_int32_t *, size_t);
466:
467: static __inline void
468: bus_space_read_region_stream_2(tag, bsh, offset, addr, count)
469: bus_space_tag_t tag;
470: bus_space_handle_t bsh;
471: bus_size_t offset;
472: u_int16_t *addr;
473: size_t count;
474: {
475: volatile u_int16_t *s;
476:
477: s = (volatile u_int16_t *)(bsh + offset);
478: while (count--)
479: *addr++ = *s++;
480: __asm__ volatile("eieio; sync");
481: }
482:
483: static __inline void
484: bus_space_read_region_stream_4(tag, bsh, offset, addr, count)
485: bus_space_tag_t tag;
486: bus_space_handle_t bsh;
487: bus_size_t offset;
488: u_int32_t *addr;
489: size_t count;
490: {
491: volatile u_int32_t *s;
492:
493: s = (volatile u_int32_t *)(bsh + offset);
494: while (count--)
495: *addr++ = *s++;
496: __asm__ volatile("eieio; sync");
497: }
498:
499: #define bus_space_read_region_stream_8 \
500: !!! bus_space_read_region_stream_8 unimplemented !!!
501:
502: /*
503: * void bus_space_write_region_N(bus_space_tag_t tag,
504: * bus_space_handle_t bsh, bus_size_t offset,
505: * const u_intN_t *addr, size_t count);
506: *
507: * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
508: * to bus space described by tag/handle starting at `offset'.
509: */
510: static __inline void bus_space_write_region_1(bus_space_tag_t,
511: bus_space_handle_t, bus_size_t, const u_int8_t *, size_t);
512: static __inline void bus_space_write_region_2(bus_space_tag_t,
513: bus_space_handle_t, bus_size_t, const u_int16_t *, size_t);
514: static __inline void bus_space_write_region_4(bus_space_tag_t,
515: bus_space_handle_t, bus_size_t, const u_int32_t *, size_t);
516:
517: static __inline void
518: bus_space_write_region_1(tag, bsh, offset, addr, count)
519: bus_space_tag_t tag;
520: bus_space_handle_t bsh;
521: bus_size_t offset;
522: const u_int8_t *addr;
523: size_t count;
524: {
525: volatile u_int8_t *d;
526:
527: d = (volatile u_int8_t *)(bsh + offset);
528: while (count--)
529: *d++ = *addr++;
530: __asm__ volatile("eieio; sync");
531: }
532:
533: static __inline void
534: bus_space_write_region_2(tag, bsh, offset, addr, count)
535: bus_space_tag_t tag;
536: bus_space_handle_t bsh;
537: bus_size_t offset;
538: const u_int16_t *addr;
539: size_t count;
540: {
541: volatile u_int16_t *d;
542:
543: d = (volatile u_int16_t *)(bsh + offset);
544: while (count--)
545: __asm__ volatile("sthbrx %0, 0, %1" ::
546: "r"(*addr++), "r"(d++));
547: __asm__ volatile("eieio; sync");
548: }
549:
550: static __inline void
551: bus_space_write_region_4(tag, bsh, offset, addr, count)
552: bus_space_tag_t tag;
553: bus_space_handle_t bsh;
554: bus_size_t offset;
555: const u_int32_t *addr;
556: size_t count;
557: {
558: volatile u_int32_t *d;
559:
560: d = (volatile u_int32_t *)(bsh + offset);
561: while (count--)
562: __asm__ volatile("stwbrx %0, 0, %1" ::
563: "r"(*addr++), "r"(d++));
564: __asm__ volatile("eieio; sync");
565: }
566:
567: #define bus_space_write_region_8 !!! bus_space_write_region_8 unimplemented !!!
568:
569: /*
570: * void bus_space_write_region_stream_N(bus_space_tag_t tag,
571: * bus_space_handle_t bsh, bus_size_t offset,
572: * const u_intN_t *addr, size_t count);
573: *
574: * Write `count' 2, 4, or 8 byte stream quantities from the buffer provided
575: * to bus space described by tag/handle starting at `offset'.
576: */
577: static __inline void bus_space_write_region_stream_2(bus_space_tag_t,
578: bus_space_handle_t, bus_size_t, const u_int16_t *, size_t);
579: static __inline void bus_space_write_region_stream_4(bus_space_tag_t,
580: bus_space_handle_t, bus_size_t, const u_int32_t *, size_t);
581:
582: static __inline void
583: bus_space_write_region_stream_2(tag, bsh, offset, addr, count)
584: bus_space_tag_t tag;
585: bus_space_handle_t bsh;
586: bus_size_t offset;
587: const u_int16_t *addr;
588: size_t count;
589: {
590: volatile u_int16_t *d;
591:
592: d = (volatile u_int16_t *)(bsh + offset);
593: while (count--)
594: *d++ = *addr++;
595: __asm__ volatile("eieio; sync");
596: }
597:
598: static __inline void
599: bus_space_write_region_stream_4(tag, bsh, offset, addr, count)
600: bus_space_tag_t tag;
601: bus_space_handle_t bsh;
602: bus_size_t offset;
603: const u_int32_t *addr;
604: size_t count;
605: {
606: volatile u_int32_t *d;
607:
608: d = (volatile u_int32_t *)(bsh + offset);
609: while (count--)
610: *d++ = *addr++;
611: __asm__ volatile("eieio; sync");
612: }
613:
614: #define bus_space_write_region_stream_8 \
615: !!! bus_space_write_region_stream_8 unimplemented !!!
616:
617: /*
618: * void bus_space_set_multi_N(bus_space_tag_t tag,
619: * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
620: * size_t count);
621: *
622: * Write the 1, 2, 4, or 8 byte value `val' to bus space described
623: * by tag/handle/offset `count' times.
624: */
625: static __inline void bus_space_set_multi_1(bus_space_tag_t,
626: bus_space_handle_t, bus_size_t, u_int8_t, size_t);
627: static __inline void bus_space_set_multi_2(bus_space_tag_t,
628: bus_space_handle_t, bus_size_t, u_int16_t, size_t);
629: static __inline void bus_space_set_multi_4(bus_space_tag_t,
630: bus_space_handle_t, bus_size_t, u_int32_t, size_t);
631:
632: static __inline void
633: bus_space_set_multi_1(tag, bsh, offset, val, count)
634: bus_space_tag_t tag;
635: bus_space_handle_t bsh;
636: bus_size_t offset;
637: u_int8_t val;
638: size_t count;
639: {
640: volatile u_int8_t *d;
641:
642: d = (volatile u_int8_t *)(bsh + offset);
643: while (count--)
644: *d = val;
645: __asm__ volatile("eieio; sync");
646: }
647:
648: static __inline void
649: bus_space_set_multi_2(tag, bsh, offset, val, count)
650: bus_space_tag_t tag;
651: bus_space_handle_t bsh;
652: bus_size_t offset;
653: u_int16_t val;
654: size_t count;
655: {
656: volatile u_int16_t *d;
657:
658: d = (volatile u_int16_t *)(bsh + offset);
659: while (count--)
660: __asm__ volatile("sthbrx %0, 0, %1" ::
661: "r"(val), "r"(d));
662: __asm__ volatile("eieio; sync");
663: }
664:
665: static __inline void
666: bus_space_set_multi_4(tag, bsh, offset, val, count)
667: bus_space_tag_t tag;
668: bus_space_handle_t bsh;
669: bus_size_t offset;
670: u_int32_t val;
671: size_t count;
672: {
673: volatile u_int32_t *d;
674:
675: d = (volatile u_int32_t *)(bsh + offset);
676: while (count--)
677: __asm__ volatile("stwbrx %0, 0, %1" ::
678: "r"(val), "r"(d));
679: __asm__ volatile("eieio; sync");
680: }
681:
682: #define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!!
683:
684: /*
685: * void bus_space_set_multi_stream_N(bus_space_tag_t tag,
686: * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
687: * size_t count);
688: *
689: * Write the 2, 4, or 8 byte stream value `val' to bus space described
690: * by tag/handle/offset `count' times.
691: */
692: static __inline void bus_space_set_multi_stream_2(bus_space_tag_t,
693: bus_space_handle_t, bus_size_t, u_int16_t, size_t);
694: static __inline void bus_space_set_multi_stream_4(bus_space_tag_t,
695: bus_space_handle_t, bus_size_t, u_int32_t, size_t);
696:
697: static __inline void
698: bus_space_set_multi_stream_2(tag, bsh, offset, val, count)
699: bus_space_tag_t tag;
700: bus_space_handle_t bsh;
701: bus_size_t offset;
702: u_int16_t val;
703: size_t count;
704: {
705: volatile u_int16_t *d;
706:
707: d = (volatile u_int16_t *)(bsh + offset);
708: while (count--)
709: *d = val;
710: __asm__ volatile("eieio; sync");
711: }
712:
713: static __inline void
714: bus_space_set_multi_stream_4(tag, bsh, offset, val, count)
715: bus_space_tag_t tag;
716: bus_space_handle_t bsh;
717: bus_size_t offset;
718: u_int32_t val;
719: size_t count;
720: {
721: volatile u_int32_t *d;
722:
723: d = (volatile u_int32_t *)(bsh + offset);
724: while (count--)
725: *d = val;
726: __asm__ volatile("eieio; sync");
727: }
728:
729: #define bus_space_set_multi_stream_8 \
730: !!! bus_space_set_multi_stream_8 unimplemented !!!
731:
732: /*
733: * void bus_space_set_region_N(bus_space_tag_t tag,
734: * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
735: * size_t count);
736: *
737: * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
738: * by tag/handle starting at `offset'.
739: */
740: static __inline void bus_space_set_region_1(bus_space_tag_t,
741: bus_space_handle_t, bus_size_t, u_int8_t, size_t);
742: static __inline void bus_space_set_region_2(bus_space_tag_t,
743: bus_space_handle_t, bus_size_t, u_int16_t, size_t);
744: static __inline void bus_space_set_region_4(bus_space_tag_t,
745: bus_space_handle_t, bus_size_t, u_int32_t, size_t);
746:
747: static __inline void
748: bus_space_set_region_1(tag, bsh, offset, val, count)
749: bus_space_tag_t tag;
750: bus_space_handle_t bsh;
751: bus_size_t offset;
752: u_int8_t val;
753: size_t count;
754: {
755: volatile u_int8_t *d;
756:
757: d = (volatile u_int8_t *)(bsh + offset);
758: while (count--)
759: *d++ = val;
760: __asm__ volatile("eieio; sync");
761: }
762:
763: static __inline void
764: bus_space_set_region_2(tag, bsh, offset, val, count)
765: bus_space_tag_t tag;
766: bus_space_handle_t bsh;
767: bus_size_t offset;
768: u_int16_t val;
769: size_t count;
770: {
771: volatile u_int16_t *d;
772:
773: d = (volatile u_int16_t *)(bsh + offset);
774: while (count--)
775: __asm__ volatile("sthbrx %0, 0, %1" ::
776: "r"(val), "r"(d++));
777: __asm__ volatile("eieio; sync");
778: }
779:
780: static __inline void
781: bus_space_set_region_4(tag, bsh, offset, val, count)
782: bus_space_tag_t tag;
783: bus_space_handle_t bsh;
784: bus_size_t offset;
785: u_int32_t val;
786: size_t count;
787: {
788: volatile u_int32_t *d;
789:
790: d = (volatile u_int32_t *)(bsh + offset);
791: while (count--)
792: __asm__ volatile("stwbrx %0, 0, %1" ::
793: "r"(val), "r"(d++));
794: __asm__ volatile("eieio; sync");
795: }
796:
797: #define bus_space_set_region_8 !!! bus_space_set_region_8 unimplemented !!!
798:
799: /*
800: * void bus_space_set_region_stream_N(bus_space_tag_t tag,
801: * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
802: * size_t count);
803: *
804: * Write `count' 2, 4, or 8 byte stream value `val' to bus space described
805: * by tag/handle starting at `offset'.
806: */
807: static __inline void bus_space_set_region_stream_2(bus_space_tag_t,
808: bus_space_handle_t, bus_size_t, u_int16_t, size_t);
809: static __inline void bus_space_set_region_stream_4(bus_space_tag_t,
810: bus_space_handle_t, bus_size_t, u_int32_t, size_t);
811:
812:
813: static __inline void
814: bus_space_set_region_stream_2(tag, bsh, offset, val, count)
815: bus_space_tag_t tag;
816: bus_space_handle_t bsh;
817: bus_size_t offset;
818: u_int16_t val;
819: size_t count;
820: {
821: volatile u_int16_t *d;
822:
823: d = (volatile u_int16_t *)(bsh + offset);
824: while (count--)
825: *d++ = val;
826: __asm__ volatile("eieio; sync");
827: }
828:
829: static __inline void
830: bus_space_set_region_stream_4(tag, bsh, offset, val, count)
831: bus_space_tag_t tag;
832: bus_space_handle_t bsh;
833: bus_size_t offset;
834: u_int32_t val;
835: size_t count;
836: {
837: volatile u_int32_t *d;
838:
839: d = (volatile u_int32_t *)(bsh + offset);
840: while (count--)
841: *d++ = val;
842: __asm__ volatile("eieio; sync");
843: }
844:
845: #define bus_space_set_region_stream_8 \
846: !!! bus_space_set_region_stream_8 unimplemented !!!
847:
848: /*
849: * void bus_space_copy_region_N(bus_space_tag_t tag,
850: * bus_space_handle_t bsh1, bus_size_t off1,
851: * bus_space_handle_t bsh2, bus_size_t off2,
852: * size_t count);
853: *
854: * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
855: * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
856: */
857:
858: static __inline void bus_space_copy_region_1(bus_space_tag_t,
859: bus_space_handle_t, bus_size_t, bus_space_handle_t,
860: bus_size_t, size_t);
861: static __inline void bus_space_copy_region_2(bus_space_tag_t,
862: bus_space_handle_t, bus_size_t, bus_space_handle_t,
863: bus_size_t, size_t);
864: static __inline void bus_space_copy_region_4(bus_space_tag_t,
865: bus_space_handle_t, bus_size_t, bus_space_handle_t,
866: bus_size_t, size_t);
867:
868: static __inline void
869: bus_space_copy_region_1(t, h1, o1, h2, o2, c)
870: bus_space_tag_t t;
871: bus_space_handle_t h1;
872: bus_size_t o1;
873: bus_space_handle_t h2;
874: bus_size_t o2;
875: size_t c;
876: {
877: bus_addr_t addr1 = h1 + o1;
878: bus_addr_t addr2 = h2 + o2;
879:
880: if (addr1 >= addr2) {
881: /* src after dest: copy forward */
882: for (; c != 0; c--, addr1++, addr2++)
883: *(volatile u_int8_t *)(addr2) =
884: *(volatile u_int8_t *)(addr1);
885: } else {
886: /* dest after src: copy backwards */
887: for (addr1 += (c - 1), addr2 += (c - 1);
888: c != 0; c--, addr1--, addr2--)
889: *(volatile u_int8_t *)(addr2) =
890: *(volatile u_int8_t *)(addr1);
891: }
892: }
893:
894: static __inline void
895: bus_space_copy_region_2(t, h1, o1, h2, o2, c)
896: bus_space_tag_t t;
897: bus_space_handle_t h1;
898: bus_size_t o1;
899: bus_space_handle_t h2;
900: bus_size_t o2;
901: size_t c;
902: {
903: bus_addr_t addr1 = h1 + o1;
904: bus_addr_t addr2 = h2 + o2;
905:
906: if (addr1 >= addr2) {
907: /* src after dest: copy forward */
908: for (; c != 0; c--, addr1 += 2, addr2 += 2)
909: *(volatile u_int16_t *)(addr2) =
910: *(volatile u_int16_t *)(addr1);
911: } else {
912: /* dest after src: copy backwards */
913: for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1);
914: c != 0; c--, addr1 -= 2, addr2 -= 2)
915: *(volatile u_int16_t *)(addr2) =
916: *(volatile u_int16_t *)(addr1);
917: }
918: }
919:
920: static __inline void
921: bus_space_copy_region_4(t, h1, o1, h2, o2, c)
922: bus_space_tag_t t;
923: bus_space_handle_t h1;
924: bus_size_t o1;
925: bus_space_handle_t h2;
926: bus_size_t o2;
927: size_t c;
928: {
929: bus_addr_t addr1 = h1 + o1;
930: bus_addr_t addr2 = h2 + o2;
931:
932: if (addr1 >= addr2) {
933: /* src after dest: copy forward */
934: for (; c != 0; c--, addr1 += 4, addr2 += 4)
935: *(volatile u_int32_t *)(addr2) =
936: *(volatile u_int32_t *)(addr1);
937: } else {
938: /* dest after src: copy backwards */
939: for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
940: c != 0; c--, addr1 -= 4, addr2 -= 4)
941: *(volatile u_int32_t *)(addr2) =
942: *(volatile u_int32_t *)(addr1);
943: }
944: }
945:
946: #define bus_space_copy_region_8 !!! bus_space_copy_region_8 unimplemented !!!
947:
948: /*
949: * Bus read/write barrier methods.
950: *
951: * void bus_space_barrier(bus_space_tag_t tag,
952: * bus_space_handle_t bsh, bus_size_t offset,
953: * bus_size_t len, int flags);
954: *
955: */
956: #define bus_space_barrier(t, h, o, l, f) \
957: ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
958: #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
959: #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
960:
961: /*
962: * Bus DMA methods.
963: */
964:
965: /*
966: * Flags used in various bus DMA methods.
967: */
968: #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
969: #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
970: #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
971: #define BUS_DMAMEM_NOSYNC 0x004
972: #define BUS_DMA_COHERENT 0x008 /* hint: map memory DMA coherent */
973: #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
974: #define BUS_DMA_BUS2 0x020
975: #define BUS_DMA_BUS3 0x040
976: #define BUS_DMA_BUS4 0x080
977: #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
978: #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
979: #define BUS_DMA_STREAMING 0x400 /* hint: sequential, unidirectional */
980:
981: /* Forwards needed by prototypes below. */
982: struct mbuf;
983: struct uio;
984:
985: #define BUS_DMASYNC_PREREAD 0x01
986: #define BUS_DMASYNC_POSTREAD 0x02
987: #define BUS_DMASYNC_PREWRITE 0x04
988: #define BUS_DMASYNC_POSTWRITE 0x08
989:
990: typedef struct powerpc_bus_dma_tag *bus_dma_tag_t;
991: typedef struct powerpc_bus_dmamap *bus_dmamap_t;
992:
993: /*
994: * bus_dma_segment_t
995: *
996: * Describes a single contiguous DMA transaction. Values
997: * are suitable for programming into DMA registers.
998: */
999: struct powerpc_bus_dma_segment {
1000: bus_addr_t ds_addr; /* DMA address */
1001: bus_size_t ds_len; /* length of transfer */
1002: };
1003: typedef struct powerpc_bus_dma_segment bus_dma_segment_t;
1004:
1005: /*
1006: * bus_dma_tag_t
1007: *
1008: * A machine-dependent opaque type describing the implementation of
1009: * DMA for a given bus.
1010: */
1011:
1012: struct powerpc_bus_dma_tag {
1013: /*
1014: * The `bounce threshold' is checked while we are loading
1015: * the DMA map. If the physical address of the segment
1016: * exceeds the threshold, an error will be returned. The
1017: * caller can then take whatever action is necessary to
1018: * bounce the transfer. If this value is 0, it will be
1019: * ignored.
1020: */
1021: bus_addr_t _bounce_thresh;
1022:
1023: /*
1024: * DMA mapping methods.
1025: */
1026: int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
1027: bus_size_t, bus_size_t, int, bus_dmamap_t *);
1028: void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
1029: int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
1030: bus_size_t, struct proc *, int);
1031: int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
1032: struct mbuf *, int);
1033: int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
1034: struct uio *, int);
1035: int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
1036: bus_dma_segment_t *, int, bus_size_t, int);
1037: void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
1038: void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
1039: bus_addr_t, bus_size_t, int);
1040:
1041: /*
1042: * DMA memory utility functions.
1043: */
1044: int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
1045: bus_size_t, bus_dma_segment_t *, int, int *, int);
1046: void (*_dmamem_free)(bus_dma_tag_t,
1047: bus_dma_segment_t *, int);
1048: int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
1049: int, size_t, caddr_t *, int);
1050: void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
1051: paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
1052: int, off_t, int, int);
1053: };
1054:
1055: #define bus_dmamap_create(t, s, n, m, b, f, p) \
1056: (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
1057: #define bus_dmamap_destroy(t, p) \
1058: (*(t)->_dmamap_destroy)((t), (p))
1059: #define bus_dmamap_load(t, m, b, s, p, f) \
1060: (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
1061: #define bus_dmamap_load_mbuf(t, m, b, f) \
1062: (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
1063: #define bus_dmamap_load_uio(t, m, u, f) \
1064: (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
1065: #define bus_dmamap_load_raw(t, m, sg, n, s, f) \
1066: (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
1067: #define bus_dmamap_unload(t, p) \
1068: (*(t)->_dmamap_unload)((t), (p))
1069: #define bus_dmamap_sync(t, p, a, l, o) \
1070: (void)((t)->_dmamap_sync ? \
1071: (*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
1072:
1073: #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
1074: (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
1075: #define bus_dmamem_free(t, sg, n) \
1076: (*(t)->_dmamem_free)((t), (sg), (n))
1077: #define bus_dmamem_map(t, sg, n, s, k, f) \
1078: (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
1079: #define bus_dmamem_unmap(t, k, s) \
1080: (*(t)->_dmamem_unmap)((t), (k), (s))
1081: #define bus_dmamem_mmap(t, sg, n, o, p, f) \
1082: (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
1083:
1084: /*
1085: * bus_dmamap_t
1086: *
1087: * Describes a DMA mapping.
1088: */
1089: struct powerpc_bus_dmamap {
1090: /*
1091: * PRIVATE MEMBERS: not for use by machine-independent code.
1092: */
1093: bus_size_t _dm_size; /* largest DMA transfer mappable */
1094: int _dm_segcnt; /* number of segs this map can map */
1095: bus_size_t _dm_maxsegsz; /* largest possible segment */
1096: bus_size_t _dm_boundary; /* don't cross this */
1097: bus_addr_t _dm_bounce_thresh; /* bounce threshold; see tag */
1098: int _dm_flags; /* misc. flags */
1099:
1100: void *_dm_cookie; /* cookie for bus-specific functions */
1101:
1102: /*
1103: * PUBLIC MEMBERS: these are used by machine-independent code.
1104: */
1105: bus_size_t dm_mapsize; /* size of the mapping */
1106: int dm_nsegs; /* # valid segments in mapping */
1107: bus_dma_segment_t dm_segs[1]; /* segments; variable length */
1108: };
1109:
1110: #ifdef _POWERPC_BUS_DMA_PRIVATE
1111: int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
1112: bus_size_t, int, bus_dmamap_t *);
1113: void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
1114: int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
1115: bus_size_t, struct proc *, int);
1116: int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t,
1117: struct mbuf *, int);
1118: int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t,
1119: struct uio *, int);
1120: int _bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
1121: bus_dma_segment_t *, int, bus_size_t, int);
1122: void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
1123: void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
1124: bus_size_t, int);
1125:
1126: int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
1127: bus_size_t alignment, bus_size_t boundary,
1128: bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
1129: void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs,
1130: int nsegs);
1131: int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
1132: int nsegs, size_t size, caddr_t *kvap, int flags);
1133: void _bus_dmamem_unmap(bus_dma_tag_t tag, caddr_t kva,
1134: size_t size);
1135: paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
1136: int nsegs, off_t off, int prot, int flags);
1137:
1138: int _bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
1139: bus_size_t alignment, bus_size_t boundary,
1140: bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
1141: paddr_t low, paddr_t high);
1142: #endif /* _POWERPC_BUS_DMA_PRIVATE */
1143: #endif /* _POWERPC_BUS_H_ */
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