Annotation of sys/arch/mvmeppc/dev/ravenvar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ravenvar.h,v 1.3 2004/01/29 10:58:06 miod Exp $ */
2:
3: /*
4: * Copyright (c) 2001 Steve Murphree, Jr.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed under OpenBSD for RTMX Inc
17: * by Per Fogelstrom, Opsycon AB.
18: * 4. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
22: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
25: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: *
33: *
34: * Motorola 'Raven' PowerPC to PCI bridge controller
35: */
36:
37: #ifndef _DEV_RAVENVAR_H_
38: #define _DEV_RAVENVAR_H_
39:
40: #define MPCIC_BASE 0xFC000000
41: #define MPCIC_SIZE 0x00022000
42:
43: #define MPCIC_FEATURE 0x01000
44: #define MPCIC_GCR 0x01020
45: #define MPCIC_VID 0x01080
46: #define MPCIC_PINIT 0x01090
47: #define MPCIC_IPI0 0x010A0
48: #define MPCIC_IPI1 0x010B0
49: #define MPCIC_IPI2 0x010C0
50: #define MPCIC_IPI3 0x010D0
51: #define MPCIC_SP 0x010E0
52: #define MPCIC_TFR 0x010F0
53: #define MPCIC_T0CC 0x01100
54: #define MPCIC_T0BC 0x01110
55: #define MPCIC_T0VP 0x01120
56: #define MPCIC_T0D 0x01130
57: #define MPCIC_T1CC 0x01140
58: #define MPCIC_T1BC 0x01150
59: #define MPCIC_T1VP 0x01160
60: #define MPCIC_T1D 0x01170
61: #define MPCIC_T2CC 0x01180
62: #define MPCIC_T2BC 0x01190
63: #define MPCIC_T2VP 0x011A0
64: #define MPCIC_T2D 0x011B0
65: #define MPCIC_T3CC 0x011C0
66: #define MPCIC_T3BC 0x011D0
67: #define MPCIC_T3VP 0x011E0
68: #define MPCIC_T3D 0x011F0
69: #define MPCIC_INT0VP 0x10000
70: #define MPCIC_INT0D 0x10010
71: #define MPCIC_INT1VP 0x10020
72: #define MPCIC_INT1D 0x10030
73: #define MPCIC_INT2VP 0x10040
74: #define MPCIC_INT2D 0x10050
75: #define MPCIC_INT3VP 0x10060
76: #define MPCIC_INT3D 0x10070
77: #define MPCIC_INT4VP 0x10080
78: #define MPCIC_INT4D 0x10090
79: #define MPCIC_INT5VP 0x100A0
80: #define MPCIC_INT5D 0x100B0
81: #define MPCIC_INT6VP 0x100C0
82: #define MPCIC_INT6D 0x100D0
83: #define MPCIC_INT7VP 0x100E0
84: #define MPCIC_INT7D 0x100F0
85: #define MPCIC_INT8VP 0x10100
86: #define MPCIC_INT8D 0x10110
87: #define MPCIC_INT9VP 0x10120
88: #define MPCIC_INT9D 0x10130
89: #define MPCIC_INT10VP 0x10140
90: #define MPCIC_INT10D 0x10150
91: #define MPCIC_INT11VP 0x10160
92: #define MPCIC_INT11D 0x10170
93: #define MPCIC_INT12VP 0x10180
94: #define MPCIC_INT12D 0x10190
95: #define MPCIC_INT13VP 0x101A0
96: #define MPCIC_INT13D 0x101B0
97: #define MPCIC_INT14VP 0x101C0
98: #define MPCIC_INT14D 0x101D0
99: #define MPCIC_INT15VP 0x101E0
100: #define MPCIC_INT15D 0x101F0
101: #define MPCIC_EVP 0x10200
102: #define MPCIC_ED 0x10210
103: #define MPCIC_P0_IPI0_D 0x20040
104: #define MPCIC_P0_IPI1_D 0x20050
105: #define MPCIC_P0_IPI2_D 0x20060
106: #define MPCIC_P0_IPI3_D 0x20070
107: #define MPCIC_P0_TP 0x20080
108: #define MPCIC_P0_IACK 0x200A0
109: #define MPCIC_P0_EOI 0x200B0
110: #define MPCIC_P1_IPI0_D 0x21040
111: #define MPCIC_P1_IPI1_D 0x21050
112: #define MPCIC_P1_IPI2_D 0x21060
113: #define MPCIC_P1_IPI3_D 0x21070
114: #define MPCIC_P1_TP 0x21080
115: #define MPCIC_P1_IACK 0x210A0
116: #define MPCIC_P1_EOI 0x210B0
117:
118: #define PROC0 0x01
119: #define PROC1 0x02
120:
121: #define GCR_M 0x04
122: #define VP_MASKED 0x00000080
123: #define VP_LEVEL 0x00004000
124: #define VP_POL 0x00008000
125: #define VP_VEC(x) ((x) << 24)
126: #define VP_PRI(x) ((x) << 8)
127:
128: struct mpic_feature {
129: unsigned int res1 : 4,
130: nirq : 12,
131: res2 : 3,
132: ncpu : 5,
133: vid : 8;
134: };
135:
136: struct mpic_gcr {
137: unsigned int reset : 1,
138: res1 : 1,
139: cmode : 1,
140: res2 : 29;
141: };
142:
143: struct mpic_vid {
144: unsigned int res1 : 8,
145: stp : 8,
146: res2 : 16;
147: };
148:
149:
150: struct mpic_ipivp {
151: unsigned int masked : 1,
152: act : 1,
153: res1 : 10,
154: pri : 4,
155: res2 : 8,
156: vec : 8;
157: };
158:
159: struct mpic_timer_count {
160: unsigned int toggle : 1,
161: count : 31;
162: };
163:
164: struct mpic_timer_bcount {
165: unsigned int inhib : 1,
166: count : 31;
167: };
168:
169: struct mpic_timer_vp {
170: unsigned int masked : 1,
171: act : 1,
172: res1 : 10,
173: pri : 4,
174: res2 : 8,
175: vec : 8;
176: };
177:
178: struct mpic_timer {
179: struct mpic_timer_count *cr;
180: struct mpic_timer_bcount *bcr;
181: struct mpic_timer_vp *vp;
182: unsigned char *dest;
183: };
184:
185: struct mpic_ext_vp {
186: unsigned int masked : 1,
187: act : 1,
188: res1 : 6,
189: polarity : 1,
190: sense : 1,
191: res2 : 2,
192: pri : 4,
193: res3 : 8,
194: vec : 8;
195: };
196:
197: struct mpic_ext_intr {
198: volatile unsigned int *vp;
199: volatile unsigned char *dest;
200: };
201:
202: struct mpic_err_vp {
203: unsigned int masked : 1,
204: act : 1,
205: res3 : 7,
206: sense : 1,
207: res2 : 2,
208: pri : 4,
209: res1 : 8,
210: vec : 8;
211: };
212:
213: #if 1
214: struct raven_reg {
215: struct mpic_feature *feature;
216: unsigned int *gcr;
217: struct mpic_vid *vid;
218: char *p_init;
219: struct mpic_ipivp *ipi[4];
220: char *sp;
221: unsigned int *timer_freq;
222: struct mpic_timer timer[4];
223: /* external interrupt configuration registers */
224: struct mpic_ext_intr extint[16];
225: unsigned int *p0_ipi0d;
226: unsigned int *p0_ipi1d;
227: unsigned int *p0_ipi2d;
228: unsigned int *p0_ipi3d;
229: unsigned int *p1_ipi0d;
230: unsigned int *p1_ipi1d;
231: unsigned int *p1_ipi2d;
232: unsigned int *p1_ipi3d;
233: /* task priority registers (IPL) */
234: unsigned char *tp[2];
235: /* interrupt acknowledge registers */
236: volatile unsigned char *iack[2];
237: /* end of interrupt registers */
238: volatile unsigned char *eio[2];
239: };
240:
241: #else
242: struct raven_reg {
243: struct mpic_feature *feature = (struct mpic_feature *)MPCIC_FEATURE;
244: struct mpic_gcr *gcr = (struct mpic_gcr *)MPCIC_GCR;
245: struct mpic_vid *vid = (struct mpic_vid *)MPCIC_VID;
246: char *p_init = (char *)MPCIC_PINIT;
247: #if 0
248: struct mpic_ipivp *ipi0 = (struct mpic_ipivp *)MPCIC_IPI0;
249: struct mpic_ipivp *ipi1 = (struct mpic_ipivp *)MPCIC_IPI1;
250: struct mpic_ipivp *ipi2 = (struct mpic_ipivp *)MPCIC_IPI2;
251: struct mpic_ipivp *ipi3 = (struct mpic_ipivp *)MPCIC_IPI3;
252: #else
253: struct mpic_ipivp *ipi[4] = {
254: (struct mpic_ipivp *)MPCIC_IPI0,
255: (struct mpic_ipivp *)MPCIC_IPI1,
256: (struct mpic_ipivp *)MPCIC_IPI2,
257: (struct mpic_ipivp *)MPCIC_IPI3,
258: };
259: #endif
260: char *sp = (char *)MPCIC_SP;
261: unsigned int *timer_freq = (unsigned int *)MPCIC_TFR;
262: #if 1
263: struct mpic_timer timer[4] = {
264: {(struct mpic_timer_count *)MPCIC_T0CC,
265: (struct mpic_timer_bcount *)MPCIC_T0BC,
266: (struct mpic_timer_vp *)MPCIC_T0VP,
267: (unsigned char *)MPCIC_T0D},
268: {(struct mpic_timer_count *)MPCIC_T1CC,
269: (struct mpic_timer_bcount *)MPCIC_T1BC,
270: (struct mpic_timer_vp *)MPCIC_T1VP,
271: (unsigned char *)MPCIC_T1D},
272: {(struct mpic_timer_count *)MPCIC_T2CC,
273: (struct mpic_timer_bcount *)MPCIC_T2BC,
274: (struct mpic_timer_vp *)MPCIC_T2VP,
275: (unsigned char *)MPCIC_T2D},
276: {(struct mpic_timer_count *)MPCIC_T3CC,
277: (struct mpic_timer_bcount *)MPCIC_T3BC,
278: (struct mpic_timer_vp *)MPCIC_T3VP,
279: (unsigned char *)MPCIC_T3D}
280: };
281: #else
282: struct mpic_timer_count *t0c = (struct mpic_timer_count *)MPCIC_T0CC;
283: struct mpic_timer_bcount *t0bc = (struct mpic_timer_bcount *)MPCIC_T0BC;
284: struct mpic_timer_vp *t0vp = (struct mpic_timer_vp *)MPCIC_T0VP;
285: unsigned int *t0d = (unsigned int *)MPCIC_T0D;
286: struct mpic_timer_count *t1c = (struct mpic_timer_count *)MPCIC_T1CC;
287: struct mpic_timer_bcount *t1bc = (struct mpic_timer_bcount *)MPCIC_T1BC;
288: struct mpic_timer_vp *t1vp = (struct mpic_timer_vp *)MPCIC_T1VP;
289: unsigned int *t1d = (unsigned int *)MPCIC_T1D;
290: struct mpic_timer_count *t2c = (struct mpic_timer_count *)MPCIC_T2CC;
291: struct mpic_timer_bcount *t2bc = (struct mpic_timer_bcount *)MPCIC_T2BC;
292: struct mpic_timer_vp *t2vp = (struct mpic_timer_vp *)MPCIC_T2VP;
293: unsigned int *t2d = (unsigned int *)MPCIC_T2D;
294: struct mpic_timer_count *t3c = (struct mpic_timer_count *)MPCIC_T3CC;
295: struct mpic_timer_bcount *t3bc = (struct mpic_timer_bcount *)MPCIC_T3BC;
296: struct mpic_timer_vp *t3vp = (struct mpic_timer_vp *)MPCIC_T3VP;
297: unsigned int *t3d = (unsigned int *)MPCIC_T3D;
298: #endif
299:
300: #if 1
301: /* external interrupt configuration registers */
302: struct mpic_ext_intr extint[16] = {
303: {(struct mpic_ext_vp *)MPCIC_INT0VP, (unsigned char *)MPCIC_INT0D},
304: {(struct mpic_ext_vp *)MPCIC_INT1VP, (unsigned char *)MPCIC_INT1D},
305: {(struct mpic_ext_vp *)MPCIC_INT2VP, (unsigned char *)MPCIC_INT2D},
306: {(struct mpic_ext_vp *)MPCIC_INT3VP, (unsigned char *)MPCIC_INT3D},
307: {(struct mpic_ext_vp *)MPCIC_INT4VP, (unsigned char *)MPCIC_INT4D},
308: {(struct mpic_ext_vp *)MPCIC_INT5VP, (unsigned char *)MPCIC_INT5D},
309: {(struct mpic_ext_vp *)MPCIC_INT6VP, (unsigned char *)MPCIC_INT6D},
310: {(struct mpic_ext_vp *)MPCIC_INT7VP, (unsigned char *)MPCIC_INT7D},
311: {(struct mpic_ext_vp *)MPCIC_INT8VP, (unsigned char *)MPCIC_INT8D},
312: {(struct mpic_ext_vp *)MPCIC_INT9VP, (unsigned char *)MPCIC_INT9D},
313: {(struct mpic_ext_vp *)MPCIC_INT1VP, (unsigned char *)MPCIC_INT10D},
314: {(struct mpic_ext_vp *)MPCIC_INT11VP, (unsigned char *)MPCIC_INT11D},
315: {(struct mpic_ext_vp *)MPCIC_INT12VP, (unsigned char *)MPCIC_INT12D},
316: {(struct mpic_ext_vp *)MPCIC_INT13VP, (unsigned char *)MPCIC_INT13D},
317: {(struct mpic_ext_vp *)MPCIC_INT14VP, (unsigned char *)MPCIC_INT14D},
318: {(struct mpic_ext_vp *)MPCIC_INT16VP, (unsigned char *)MPCIC_INT15D}
319: };
320: #else
321: struct mpic_ext_vp *ext0vp = (struct mpic_ext_vp *)MPCIC_INT0VP;
322: unsigned int *ext0d = (unsigned int *)MPCIC_INT0D;
323: struct mpic_ext_vp *ext1vp = (struct mpic_ext_vp *)MPCIC_INT1VP;
324: unsigned int *ext1d = (unsigned int *)MPCIC_INT1D;
325: struct mpic_ext_vp *ext2vp = (struct mpic_ext_vp *)MPCIC_INT2VP;
326: unsigned int *ext2d = (unsigned int *)MPCIC_INT2D;
327: struct mpic_ext_vp *ext3vp = (struct mpic_ext_vp *)MPCIC_INT3VP;
328: unsigned int *ext3d = (unsigned int *)MPCIC_INT3D;
329: struct mpic_ext_vp *ext4vp = (struct mpic_ext_vp *)MPCIC_INT4VP;
330: unsigned int *ext4d = (unsigned int *)MPCIC_INT4D;
331: struct mpic_ext_vp *ext5vp = (struct mpic_ext_vp *)MPCIC_INT5VP;
332: unsigned int *ext5d = (unsigned int *)MPCIC_INT5D;
333: struct mpic_ext_vp *ext6vp = (struct mpic_ext_vp *)MPCIC_INT6VP;
334: unsigned int *ext6d = (unsigned int *)MPCIC_INT6D;
335: struct mpic_ext_vp *ext7vp = (struct mpic_ext_vp *)MPCIC_INT7VP;
336: unsigned int *ext7d = (unsigned int *)MPCIC_INT7D;
337: struct mpic_ext_vp *ext8vp = (struct mpic_ext_vp *)MPCIC_INT8VP;
338: unsigned int *ext8d = (unsigned int *)MPCIC_INT8D;
339: struct mpic_ext_vp *ext9vp = (struct mpic_ext_vp *)MPCIC_INT9VP;
340: unsigned int *ext9d = (unsigned int *)MPCIC_INT9D;
341: struct mpic_ext_vp *ext10vp = (struct mpic_ext_vp *)MPCIC_INT10VP;
342: unsigned int *ext10d = (unsigned int *)MPCIC_INT10D;
343: struct mpic_ext_vp *ext11vp = (struct mpic_ext_vp *)MPCIC_INT11VP;
344: unsigned int *ext11d = (unsigned int *)MPCIC_INT11D;
345: struct mpic_ext_vp *ext12vp = (struct mpic_ext_vp *)MPCIC_INT12VP;
346: unsigned int *ext12d = (unsigned int *)MPCIC_INT12D;
347: struct mpic_ext_vp *ext13vp = (struct mpic_ext_vp *)MPCIC_INT13VP;
348: unsigned int *ext13d = (unsigned int *)MPCIC_INT13D;
349: struct mpic_ext_vp *ext14vp = (struct mpic_ext_vp *)MPCIC_INT14VP;
350: unsigned int *ext14d = (unsigned int *)MPCIC_INT14D;
351: struct mpic_ext_vp *ext15vp = (struct mpic_ext_vp *)MPCIC_INT15VP;
352: unsigned int *ext15d = (unsigned int *)MPCIC_INT15D;
353: struct mpic_err_vp *errvp = (struct mpic_err_vp *)MPCIC_EVP;
354: unsigned int *errd = (unsigned int *)MPCIC_ED;
355: #endif
356: unsigned int *p0_ipi0d = (unsigned int *)MPCIC_P0_IPI0_D;
357: unsigned int *p0_ipi1d = (unsigned int *)MPCIC_P0_IPI1_D;
358: unsigned int *p0_ipi2d = (unsigned int *)MPCIC_P0_IPI2_D;
359: unsigned int *p0_ipi3d = (unsigned int *)MPCIC_P0_IPI3_D;
360: unsigned int *p1_ipi0d = (unsigned int *)MPCIC_P1_IPI0_D;
361: unsigned int *p1_ipi1d = (unsigned int *)MPCIC_P1_IPI1_D;
362: unsigned int *p1_ipi2d = (unsigned int *)MPCIC_P1_IPI2_D;
363: unsigned int *p1_ipi3d = (unsigned int *)MPCIC_P1_IPI3_D;
364:
365: /* task priority registers (IPL) */
366: unsigned char *tp[2] = {
367: (unsigned char *)MPCIC_P0_TP,
368: (unsigned char *)MPCIC_P1_TP
369: };
370: /* interrupt acknowledge registers */
371: volatile unsigned char *iack[2] = {
372: (volatile unsigned char *)MPCIC_P0_IACK,
373: (volatile unsigned char *)MPCIC_P1_IACK
374: };
375: /* end of interrupt registers */
376: volatile unsigned char *eio[2] = {
377: (volatile unsigned char *)MPCIC_P0_EOI,
378: (volatile unsigned char *)MPCIC_P1_EOI,
379: };
380: }
381: #endif
382:
383: struct raven_softc {
384: struct device sc_dev;
385: u_int8_t *sc_regs;
386: };
387:
388: #endif /* _DEV_RAVENVAR_H_ */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to ravenvar.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / mvmeppc / dev