Annotation of sys/arch/mvme88k/mvme88k/m187_machdep.c, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: m187_machdep.c,v 1.15 2007/05/14 16:59:43 miod Exp $ */
! 2: /*
! 3: * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
! 4: * Copyright (c) 1996 Nivas Madhur
! 5: * All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: * 3. All advertising materials mentioning features or use of this software
! 16: * must display the following acknowledgement:
! 17: * This product includes software developed by Nivas Madhur.
! 18: * 4. The name of the author may not be used to endorse or promote products
! 19: * derived from this software without specific prior written permission
! 20: *
! 21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 22: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 23: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 24: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 25: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 26: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 27: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 28: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 29: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 30: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 31: *
! 32: */
! 33: /*
! 34: * Mach Operating System
! 35: * Copyright (c) 1993-1991 Carnegie Mellon University
! 36: * Copyright (c) 1991 OMRON Corporation
! 37: * All Rights Reserved.
! 38: *
! 39: * Permission to use, copy, modify and distribute this software and its
! 40: * documentation is hereby granted, provided that both the copyright
! 41: * notice and this permission notice appear in all copies of the
! 42: * software, derivative works or modified versions, and any portions
! 43: * thereof, and that both notices appear in supporting documentation.
! 44: *
! 45: */
! 46:
! 47: #include <sys/param.h>
! 48: #include <sys/systm.h>
! 49: #include <sys/kernel.h>
! 50: #include <sys/errno.h>
! 51:
! 52: #include <uvm/uvm_extern.h>
! 53:
! 54: #include <machine/asm_macro.h>
! 55: #include <machine/cmmu.h>
! 56: #include <machine/cpu.h>
! 57: #include <machine/reg.h>
! 58: #include <machine/trap.h>
! 59: #include <machine/m88100.h>
! 60: #include <machine/mvme187.h>
! 61:
! 62: #include <mvme88k/dev/memcreg.h>
! 63: #include <mvme88k/mvme88k/clockvar.h>
! 64:
! 65: void m187_bootstrap(void);
! 66: void m187_ext_int(u_int, struct trapframe *);
! 67: u_int m187_getipl(void);
! 68: vaddr_t m187_memsize(void);
! 69: u_int m187_raiseipl(u_int);
! 70: u_int m187_setipl(u_int);
! 71: void m187_startup(void);
! 72:
! 73: vaddr_t bugromva;
! 74:
! 75: /*
! 76: * Figure out how much memory is available, by querying the memory controllers.
! 77: */
! 78: vaddr_t
! 79: m187_memsize()
! 80: {
! 81: struct memcreg *memc;
! 82: vaddr_t x;
! 83:
! 84: memc = (struct memcreg *)MEM_CTLR;
! 85: x = MEMC_MEMCONF_RTOB(memc->memc_memconf);
! 86:
! 87: memc = (struct memcreg *)(MEM_CTLR + 0x100);
! 88: if (!badaddr((vaddr_t)&memc->memc_memconf, 1))
! 89: x += MEMC_MEMCONF_RTOB(memc->memc_memconf);
! 90:
! 91: return x;
! 92: }
! 93:
! 94: void
! 95: m187_startup()
! 96: {
! 97: /*
! 98: * Grab the BUGROM space that we hardwired in pmap_bootstrap
! 99: */
! 100: bugromva = BUG187_START;
! 101: uvm_map(kernel_map, (vaddr_t *)&bugromva, BUG187_SIZE,
! 102: NULL, UVM_UNKNOWN_OFFSET, 0,
! 103: UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE,
! 104: UVM_ADV_NORMAL, 0));
! 105: if (bugromva != BUG187_START)
! 106: panic("bugromva %lx: BUGROM not free", bugromva);
! 107: }
! 108:
! 109: /*
! 110: * Device interrupt handler for MVME187
! 111: */
! 112:
! 113: void
! 114: m187_ext_int(u_int v, struct trapframe *eframe)
! 115: {
! 116: int level;
! 117: struct intrhand *intr;
! 118: intrhand_t *list;
! 119: int ret;
! 120: vaddr_t ivec;
! 121: u_int8_t vec;
! 122:
! 123: level = *(u_int8_t *)M187_ILEVEL & 0x07;
! 124:
! 125: /* generate IACK and get the vector */
! 126: ivec = M187_IACK + (level << 2) + 0x03;
! 127: vec = *(volatile u_int8_t *)ivec;
! 128:
! 129: #ifdef MULTIPROCESSOR
! 130: if (eframe->tf_mask < IPL_SCHED)
! 131: __mp_lock(&kernel_lock);
! 132: #endif
! 133:
! 134: uvmexp.intrs++;
! 135:
! 136: /* block interrupts at level or lower */
! 137: m187_setipl(level);
! 138: flush_pipeline();
! 139: set_psr(get_psr() & ~PSR_IND);
! 140:
! 141: list = &intr_handlers[vec];
! 142: if (SLIST_EMPTY(list)) {
! 143: /* increment intr counter */
! 144: printf("Spurious interrupt (level %x and vec %x)\n",
! 145: level, vec);
! 146: } else {
! 147: #ifdef DEBUG
! 148: intr = SLIST_FIRST(list);
! 149: if (intr->ih_ipl != level) {
! 150: panic("Handler ipl %x not the same as level %x. "
! 151: "vec = 0x%x",
! 152: intr->ih_ipl, level, vec);
! 153: }
! 154: #endif
! 155:
! 156: /*
! 157: * Walk through all interrupt handlers in the chain for the
! 158: * given vector, calling each handler in turn, till some handler
! 159: * returns a value != 0.
! 160: */
! 161:
! 162: ret = 0;
! 163: SLIST_FOREACH(intr, list, ih_link) {
! 164: if (intr->ih_wantframe != 0)
! 165: ret = (*intr->ih_fn)((void *)eframe);
! 166: else
! 167: ret = (*intr->ih_fn)(intr->ih_arg);
! 168: if (ret != 0) {
! 169: intr->ih_count.ec_count++;
! 170: break;
! 171: }
! 172: }
! 173:
! 174: if (ret == 0) {
! 175: printf("Unclaimed interrupt (level %x and vec %x)\n",
! 176: level, vec);
! 177: }
! 178: }
! 179:
! 180: /*
! 181: * process any remaining data access exceptions before
! 182: * returning to assembler
! 183: */
! 184: if (eframe->tf_dmt0 & DMT_VALID)
! 185: m88100_trap(T_DATAFLT, eframe);
! 186:
! 187: /*
! 188: * Disable interrupts before returning to assembler, the spl will
! 189: * be restored later.
! 190: */
! 191: set_psr(get_psr() | PSR_IND);
! 192:
! 193: #ifdef MULTIPROCESSOR
! 194: if (eframe->tf_mask < IPL_SCHED)
! 195: __mp_unlock(&kernel_lock);
! 196: #endif
! 197: }
! 198:
! 199: u_int
! 200: m187_getipl(void)
! 201: {
! 202: return *(u_int8_t *)M187_IMASK & 0x07;
! 203: }
! 204:
! 205: u_int
! 206: m187_setipl(u_int level)
! 207: {
! 208: unsigned curspl;
! 209:
! 210: curspl = *(u_int8_t *)M187_IMASK & 0x07;
! 211: *(u_int8_t *)M187_IMASK = level;
! 212: return curspl;
! 213: }
! 214:
! 215: u_int
! 216: m187_raiseipl(u_int level)
! 217: {
! 218: unsigned curspl;
! 219:
! 220: curspl = *(u_int8_t *)M187_IMASK & 0x07;
! 221: if (curspl < level)
! 222: *(u_int8_t *)M187_IMASK = level;
! 223: return curspl;
! 224: }
! 225:
! 226: void
! 227: m187_bootstrap()
! 228: {
! 229: extern struct cmmu_p cmmu8820x;
! 230:
! 231: cmmu = &cmmu8820x;
! 232: md_interrupt_func_ptr = m187_ext_int;
! 233: md_getipl = m187_getipl;
! 234: md_setipl = m187_setipl;
! 235: md_raiseipl = m187_raiseipl;
! 236: md_init_clocks = m1x7_init_clocks;
! 237: }
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