Annotation of sys/arch/mvme88k/include/m88110.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: m88110.h,v 1.17 2004/06/22 04:55:35 miod Exp $ */
2:
3: #ifndef __MACHINE_M88110_H__
4: #define __MACHINE_M88110_H__
5:
6: /*
7: * 88110 CMMU definitions
8: */
9: #define CMMU_ICMD 0
10: #define CMMU_ICTL 1
11: #define CMMU_ISAR 2
12: #define CMMU_ISAP 3
13: #define CMMU_IUAP 4
14: #define CMMU_IIR 5
15: #define CMMU_IBP 6
16: #define CMMU_IPPU 7
17: #define CMMU_IPPL 8
18: #define CMMU_ISR 9
19: #define CMMU_ILAR 10
20: #define CMMU_IPAR 11
21:
22: #define CMMU_DCMD 12
23: #define CMMU_DCTL 13
24: #define CMMU_DSAR 14
25: #define CMMU_DSAP 15
26: #define CMMU_DUAP 16
27: #define CMMU_DIR 17
28: #define CMMU_DBP 18
29: #define CMMU_DPPU 19
30: #define CMMU_DPPL 20
31: #define CMMU_DSR 21
32: #define CMMU_DLAR 22
33: #define CMMU_DPAR 23
34:
35: #define CMMU_ICMD_INV_ITIC 0x001 /* Invalidate Inst Cache & TIC */
36: #define CMMU_ICMD_INV_TIC 0x002 /* Invalidate TIC */
37: #define CMMU_ICMD_INV_LINE 0x005 /* Invalidate Inst Cache Line */
38: #define CMMU_ICMD_PRB_SUPR 0x008 /* MMU Probe Supervisor */
39: #define CMMU_ICMD_PRB_USER 0x009 /* MMU Probe User */
40: #define CMMU_ICMD_INV_SATC 0x00a /* Invalidate All Supervisor ATCs */
41: #define CMMU_ICMD_INV_UATC 0x00b /* Invalidate All User ATCs */
42:
43: #define CMMU_ICTL_DID 0x8000 /* Double instruction disable */
44: #define CMMU_ICTL_PREN 0x4000 /* Branch Prediction Enable */
45: #define CMMU_ICTL_FRZ0 0x0100 /* Inst Cache Freeze Bank 0 */
46: #define CMMU_ICTL_FRZ1 0x0080 /* Inst Cache Freeze Bank 1 */
47: #define CMMU_ICTL_HTEN 0x0040 /* Hardware Table Search Enable */
48: #define CMMU_ICTL_MEN 0x0020 /* Inst MMU Enable */
49: #define CMMU_ICTL_BEN 0x0004 /* TIC Cache Enable */
50: #define CMMU_ICTL_CEN 0x0001 /* Inst Cache Enable */
51:
52: #define CMMU_ISR_TBE 0x200000 /* Table Search Bus Error */
53: #define CMMU_ISR_SI 0x100000 /* Segment Fault*/
54: #define CMMU_ISR_PI 0x080000 /* Page Fault */
55: #define CMMU_ISR_SP 0x040000 /* Supervisor Protection Violation */
56: #define CMMU_ISR_PH 0x000800 /* PATC Hit */
57: #define CMMU_ISR_BH 0x000400 /* BATC Hit */
58: #define CMMU_ISR_SU 0x000200 /* Supervisor Bit */
59: #define CMMU_ISR_BE 0x000001 /* Bus Error */
60:
61: #define CMMU_DCMD_FLUSH_PG 0x000 /* Flush Data Cache Page (sync) */
62: #define CMMU_DCMD_INV_ALL 0x001 /* Invalidate Data Cache All */
63: #define CMMU_DCMD_FLUSH_ALL 0x002 /* Flush Data Cache All (sync) */
64: #define CMMU_DCMD_FLUSH_ALL_INV 0x003 /* Flush Data Cache All (sync & inval) */
65: #define CMMU_DCMD_FLUSH_PG_INV 0x004 /* Flush Data Cache Page (sync & inval) */
66: #define CMMU_DCMD_INV_LINE 0x005 /* Invalidate Data Cache Line */
67: #define CMMU_DCMD_FLUSH_LINE 0x006 /* Flush Data Cache Line (sync)*/
68: #define CMMU_DCMD_FLUSH_LINE_INV 0x007 /* Flush Data Cache Line (sync & inval)*/
69: #define CMMU_DCMD_PRB_SUPR 0x008 /* MMU Probe Supervisor */
70: #define CMMU_DCMD_PRB_USER 0x009 /* MMU Probe User */
71: #define CMMU_DCMD_INV_SATC 0x00A /* Invalidate All Supervisor ATCs */
72: #define CMMU_DCMD_INV_UATC 0x00B /* Invalidate All User ATCs */
73:
74: #define CMMU_DCTL_RSVD7 0x40000 /* Reserved */
75: #define CMMU_DCTL_RSVD6 0x20000 /* Reserved */
76: #define CMMU_DCTL_RSVD5 0x10000 /* Reserved */
77: #define CMMU_DCTL_RSVD4 0x8000 /* Reserved */
78: #define CMMU_DCTL_RSVD3 0x4000 /* Reserved */
79: #define CMMU_DCTL_XMEM 0x2000 /* store -> load sequence */
80: #define CMMU_DCTL_DEN 0x1000 /* Decoupled Cache Access Enable */
81: #define CMMU_DCTL_FWT 0x0800 /* Force Write Through */
82: #define CMMU_DCTL_BPEN1 0x0400 /* Break Point Enable 1 */
83: #define CMMU_DCTL_BPEN0 0x0200 /* Break Point Enable 0 */
84: #define CMMU_DCTL_FRZ0 0x0100 /* Data Cache Freeze Bank 0 */
85: #define CMMU_DCTL_FRZ1 0x0080 /* Data Cache Freeze Bank 1 */
86: #define CMMU_DCTL_HTEN 0x0040 /* Hardware Table Search Enable */
87: #define CMMU_DCTL_MEN 0x0020 /* Data MMU Enable */
88: #define CMMU_DCTL_RSVD2 0x0010 /* Reserved */
89: #define CMMU_DCTL_ADS 0x0008 /* Allocat Disable */
90: #define CMMU_DCTL_RSVD1 0x0004 /* Reserved */
91: #define CMMU_DCTL_SEN 0x0002 /* Data Cache Snoop Enable */
92: #define CMMU_DCTL_CEN 0x0001 /* Data Cache Enable */
93:
94: #define CMMU_DSR_TBE 0x200000 /* Table Search Bus Error */
95: #define CMMU_DSR_SI 0x100000 /* Segment Fault*/
96: #define CMMU_DSR_PI 0x080000 /* Page Fault */
97: #define CMMU_DSR_SP 0x040000 /* Supervisor Protection Violation */
98: #define CMMU_DSR_WE 0x020000 /* Write Protection Violation */
99: #define CMMU_DSR_BPE 0x010000 /* Break Point Exception */
100: #define CMMU_DSR_PH 0x000800 /* PATC Hit */
101: #define CMMU_DSR_BH 0x000400 /* BATC Hit */
102: #define CMMU_DSR_SU 0x000200 /* Supervisor Bit */
103: #define CMMU_DSR_RW 0x000100 /* Read Bit */
104: #define CMMU_DSR_CP 0x000004 /* Copyback Error */
105: #define CMMU_DSR_WA 0x000002 /* Write-Allocate Bus Error */
106: #define CMMU_DSR_BE 0x000001 /* Bus Error */
107:
108: #define CMMU_READ 0
109: #define CMMU_WRITE 1
110: #define CMMU_DATA 1
111: #define CMMU_INST 0
112:
113: /* definitions for use of the BATC */
114: #define BATC_512K (0x00 << BATC_BLKSHIFT)
115: #define BATC_1M (0x01 << BATC_BLKSHIFT)
116: #define BATC_2M (0x03 << BATC_BLKSHIFT)
117: #define BATC_4M (0x07 << BATC_BLKSHIFT)
118: #define BATC_8M (0x0f << BATC_BLKSHIFT)
119: #define BATC_16M (0x1f << BATC_BLKSHIFT)
120: #define BATC_32M (0x3f << BATC_BLKSHIFT)
121: #define BATC_64M (0x7f << BATC_BLKSHIFT)
122:
123: #define CLINE_MASK 0x1f
124: #define CLINE_SIZE (8 * 32)
125:
126: #ifndef _LOCORE
127:
128: void set_icmd(unsigned value);
129: void set_ictl(unsigned value);
130: void set_isar(unsigned value);
131: void set_isap(unsigned value);
132: void set_iuap(unsigned value);
133: void set_iir(unsigned value);
134: void set_ibp(unsigned value);
135: void set_ippu(unsigned value);
136: void set_ippl(unsigned value);
137: void set_isr(unsigned value);
138: void set_dcmd(unsigned value);
139: void set_dctl(unsigned value);
140: void set_dsar(unsigned value);
141: void set_dsap(unsigned value);
142: void set_duap(unsigned value);
143: void set_dir(unsigned value);
144: void set_dbp(unsigned value);
145: void set_dppu(unsigned value);
146: void set_dppl(unsigned value);
147: void set_dsr(unsigned value);
148:
149: /* get routines */
150: unsigned get_icmd(void);
151: unsigned get_ictl(void);
152: unsigned get_isar(void);
153: unsigned get_isap(void);
154: unsigned get_iuap(void);
155: unsigned get_iir(void);
156: unsigned get_ibp(void);
157: unsigned get_ippu(void);
158: unsigned get_ippl(void);
159: unsigned get_isr(void);
160: unsigned get_dcmd(void);
161: unsigned get_dctl(void);
162: unsigned get_dsar(void);
163: unsigned get_dsap(void);
164: unsigned get_duap(void);
165: unsigned get_dir(void);
166: unsigned get_dbp(void);
167: unsigned get_dppu(void);
168: unsigned get_dppl(void);
169: unsigned get_dsr(void);
170:
171: /* Cache inlines */
172:
173: #define line_addr(x) (paddr_t)((x) & ~CLINE_MASK)
174: #define page_addr(x) (paddr_t)((x) & ~PAGE_MASK)
175:
176: static __inline__ void mc88110_flush_data_line(paddr_t x)
177: {
178: unsigned dctl = get_dctl();
179: if (dctl & CMMU_DCTL_CEN) {
180: set_dsar(line_addr(x));
181: set_dcmd(CMMU_DCMD_FLUSH_LINE);
182: }
183: }
184:
185: static __inline__ void mc88110_flush_data_page(paddr_t x)
186: {
187: unsigned dctl = get_dctl();
188: if (dctl & CMMU_DCTL_CEN) {
189: set_dsar(page_addr(x));
190: set_dcmd(CMMU_DCMD_FLUSH_PG);
191: }
192: }
193:
194: static __inline__ void mc88110_flush_data(void)
195: {
196: unsigned dctl = get_dctl();
197: if (dctl & CMMU_DCTL_CEN) {
198: set_dcmd(CMMU_DCMD_FLUSH_ALL);
199: }
200: }
201:
202: static __inline__ void mc88110_inval_data_line(paddr_t x)
203: {
204: set_dsar(line_addr(x));
205: set_dcmd(CMMU_DCMD_INV_LINE);
206: }
207:
208: static __inline__ void mc88110_inval_data(void)
209: {
210: set_dcmd(CMMU_DCMD_INV_ALL);
211: }
212:
213: static __inline__ void mc88110_sync_data_line(paddr_t x)
214: {
215: unsigned dctl = get_dctl();
216: if (dctl & CMMU_DCTL_CEN) {
217: set_dsar(line_addr(x));
218: set_dcmd(CMMU_DCMD_FLUSH_LINE_INV);
219: }
220: }
221:
222: static __inline__ void mc88110_sync_data_page(paddr_t x)
223: {
224: unsigned dctl = get_dctl();
225: if (dctl & CMMU_DCTL_CEN) {
226: set_dsar(page_addr(x));
227: set_dcmd(CMMU_DCMD_FLUSH_PG_INV);
228: }
229: }
230:
231: static __inline__ void mc88110_sync_data(void)
232: {
233: unsigned dctl = get_dctl();
234: if (dctl & CMMU_DCTL_CEN) {
235: set_dcmd(CMMU_DCMD_FLUSH_ALL_INV);
236: }
237: }
238:
239: static __inline__ void mc88110_inval_inst_line(paddr_t x)
240: {
241: set_isar(line_addr(x));
242: set_icmd(CMMU_ICMD_INV_LINE);
243: }
244:
245: static __inline__ void mc88110_inval_inst(void)
246: {
247: set_icmd(CMMU_ICMD_INV_ITIC);
248: }
249:
250: #endif /* _LOCORE */
251: #endif /* __MACHINE_M88110_H__ */
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