Annotation of sys/arch/mvme88k/dev/vsvar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: vsvar.h,v 1.18 2005/12/27 21:38:13 miod Exp $ */
2: /*
3: * Copyright (c) 2004, Miodrag Vallat.
4: * Copyright (c) 1999 Steve Murphree, Jr.
5: * Copyright (c) 1990 The Regents of the University of California.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to Berkeley by
9: * Van Jacobson of Lawrence Berkeley Laboratory.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. Neither the name of the University nor the names of its contributors
20: * may be used to endorse or promote products derived from this software
21: * without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33: * SUCH DAMAGE.
34: */
35: #ifndef _VSVAR_H_
36: #define _VSVAR_H_
37:
38: /*
39: * The largest single request will be MAXPHYS bytes which will require
40: * at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of
41: * the buffer pages are physically contiguous (MAXPHYS/NBPG) and the
42: * buffer is not page aligned (+1).
43: */
44: #define DMAMAXIO (MAXPHYS/NBPG+1)
45: #define OFF(x) (u_int16_t)(x)
46:
47: /*
48: * scatter/gather structures
49: */
50:
51: typedef struct {
52: union {
53: unsigned short bytes :16;
54: #define MAX_SG_BLOCK_SIZE (1<<16)
55: struct {
56: unsigned short :8;
57: unsigned short gather:8;
58: } scatter;
59: } count;
60: u_int16_t addrhi, addrlo; /* split due to alignment */
61: unsigned short link:1;
62: unsigned short :3;
63: unsigned short transfer_type:2;
64: #define SHORT_TRANSFER 0x1
65: #define LONG_TRANSFER 0x2
66: #define SCATTER_GATTER_LIST_IN_SHORT_IO 0x3
67: unsigned short memory_type:2;
68: #define NORMAL_TYPE 0x0
69: #define BLOCK_MODE 0x1
70: unsigned short address_modifier:8;
71: } sg_list_element_t;
72:
73: typedef sg_list_element_t * scatter_gather_list_t;
74:
75: #define MAX_SG_ELEMENTS 64
76:
77: struct m328_sg {
78: struct m328_sg *up;
79: int elements;
80: int level;
81: struct m328_sg *down[MAX_SG_ELEMENTS];
82: sg_list_element_t list[MAX_SG_ELEMENTS];
83: };
84:
85: typedef struct m328_sg *M328_SG;
86:
87: struct vs_cb {
88: struct scsi_xfer *cb_xs;
89: u_int cb_q;
90: M328_SG cb_sg;
91: };
92:
93: struct vs_softc {
94: struct device sc_dev;
95: paddr_t sc_paddr;
96: bus_space_tag_t sc_iot;
97: bus_space_handle_t sc_ioh;
98: struct intrhand sc_ih_e, sc_ih_n;
99: char sc_intrname_e[16 + 4];
100: int sc_ipl;
101: int sc_evec, sc_nvec;
102: int sc_id[2];
103: struct scsi_link sc_link[2];
104: struct vs_cb sc_cb[NUM_WQ];
105: };
106:
107: /* Access macros */
108:
109: #define vs_read(w,o) \
110: bus_space_read_##w (sc->sc_iot, sc->sc_ioh, (o))
111: #define vs_write(w,o,v) \
112: bus_space_write_##w (sc->sc_iot, sc->sc_ioh, (o), (v))
113: #define vs_bzero(o,s) \
114: bus_space_set_region_2(sc->sc_iot, sc->sc_ioh, (o), 0, (s) / 2)
115:
116: #define cib_read(w,o) vs_read(w, sh_CIB + (o))
117: #define cib_write(w,o,v) vs_write(w, sh_CIB + (o), (v))
118: #define crb_read(w,o) vs_read(w, sh_CRB + (o))
119: #define crb_write(w,o,v) vs_write(w, sh_CRB + (o), (v))
120: #define csb_read(w,o) vs_read(w, sh_CSS + (o))
121: #define mce_read(w,o) vs_read(w, sh_MCE + (o))
122: #define mce_write(w,o,v) vs_write(w, sh_MCE + (o), (v))
123: #define mce_iopb_read(w,o) vs_read(w, sh_MCE_IOPB + (o))
124: #define mce_iopb_write(w,o,v) vs_write(w, sh_MCE_IOPB + (o), (v))
125: #define mcsb_read(w,o) vs_read(w, sh_MCSB + (o))
126: #define mcsb_write(w,o,v) vs_write(w, sh_MCSB + (o), (v))
127:
128: #define CRSW crb_read(2, CRB_CRSW)
129: #define CRB_CLR_DONE crb_write(2, CRB_CRSW, 0)
130: #define CRB_CLR_ER crb_write(2, CRB_CRSW, CRSW & ~M_CRSW_ER)
131:
132: #define THAW_REG mcsb_read(2, MCSB_THAW)
133: #define THAW(x) \
134: do { \
135: mcsb_write(1, MCSB_THAW, (x)); \
136: mcsb_write(1, MCSB_THAW + 1, M_THAW_TWQE); \
137: } while (0)
138:
139: #endif /* _M328VAR_H */
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