Annotation of sys/arch/mvme88k/dev/vsreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: vsreg.h,v 1.14 2006/12/21 02:28:47 krw Exp $ */
2: /*
3: * Copyright (c) 2004, Miodrag Vallat.
4: * Copyright (c) 1999 Steve Murphree, Jr.
5: * Copyright (c) 1990 The Regents of the University of California.
6: * All rights reserved.
7: *
8: * This code is derived from source contributed by Mark Bellon.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: */
34:
35: #ifndef _MVME328_REG_H_
36: #define _MVME328_REG_H_
37:
38: /*
39: * JAGUAR specific device limits
40: */
41:
42: #define JAGUAR_MIN_Q_SIZ 2
43: #define JAGUAR_MAX_CTLR_CMDS 80 /* Interphase says so */
44: #define JAGUAR_MAX_Q_SIZ (JAGUAR_MAX_CTLR_CMDS / NUM_WQ)
45:
46: /*
47: * COUGAR specific device limits
48: */
49:
50: #define COUGAR_MIN_Q_SIZ 2
51: #define COUGAR_CMDS_PER_256K 42 /* Interphase says so */
52:
53: /*
54: * Structures
55: */
56:
57: #define NUM_CQE 10
58: #define NUM_IOPB NUM_CQE
59: #define NUM_WQ 15
60:
61: /*
62: * Master Control Status Block (MCSB)
63: */
64:
65: #define MCSB_MSR 0x000000 /* master status register */
66: #define M_MSR_QFC 0x0004 /* queue flush complete */
67: #define M_MSR_BOK 0x0002 /* board OK */
68: #define M_MSR_CNA 0x0001 /* controller not available */
69: #define MCSB_MCR 0x000002 /* master control register */
70: #define M_MCR_SFEN 0x2000 /* sysfail enable */
71: #define M_MCR_RES 0x1000 /* reset controller */
72: #define M_MCR_FLQ 0x0800 /* flush queue */
73: #define M_MCR_FLQR 0x0004 /* flush queue and report */
74: #define M_MCR_SQM 0x0001 /* start queue mode */
75: #define MCSB_IQAR 0x000004 /* interrupt on queue avail */
76: #define M_IQAR_IQEA 0x8000 /* interrupt on queue entry avail */
77: #define M_IQAR_IQEH 0x4000 /* interrupt on queue half empty */
78: #define M_IQAR_ILVL 0x0700 /* interrupt lvl on queue available */
79: #define M_IQAR_IVCT 0x00ff /* interrupt vector on queue avail */
80: #define MCSB_QHDP 0x000006 /* queue head pointer */
81: #define MCSB_THAW 0x000008 /* thaw work queue */
82: #define M_THAW_TWQN 0xff00 /* thaw work queue number */
83: #define M_THAW_TWQE 0x0001 /* thaw work queue enable */
84: #define MCSB_SIZE 0x000010
85:
86: /*
87: * Host Semaphore Block (HSB)
88: */
89:
90: #define HSB_INITQ 0x000000 /* init MCE flag */
91: #define HSB_WORKQ 0x000002 /* work queue number */
92: #define HSB_MAGIC 0x000004 /* magic word */
93: #define HSB_SIZE 0x000008
94:
95: /*
96: * Controller Initialization Block (CIB)
97: */
98:
99: #define CIB_NCQE 0x000000 /* number of CQE */
100: #define CIB_BURST 0x000002 /* DMA burst count */
101: #define CIB_NVECT 0x000004 /* normal completion vector */
102: #define CIB_EVECT 0x000006 /* error completion vector */
103: #define M_VECT_ILVL 0x0700 /* Interrupt Level mask */
104: #define M_VECT_IVCT 0x00ff /* Interrupt Vector mask */
105: #define CIB_PID 0x000008 /* primary scsi bus id */
106: #define CIB_SID 0x00000a /* secondary scsi bus id */
107: #define M_PSID_DFT 0x0008 /* default ID enable */
108: #define M_PSID_ID 0x0007 /* primary/secondary SCSI ID */
109: #define CIB_CRBO 0x00000c /* CRB offset */
110: #define CIB_SELECT 0x00000e /* selection timeout in ms */
111: #define CIB_WQTIMO 0x000012 /* work queue timeout in 256ms */
112: #define CIB_VMETIMO 0x000016 /* VME timeout in 32ms */
113: #define CIB_OBMT 0x00001e /* offboard CRB mtype/xfer type/ad mod */
114: #define CIB_OBADDR 0x000020 /* host mem address for offboard CRB */
115: #define CIB_ERR_FLGS 0x000024 /* error recovery flags */
116: #define M_ERRFLGS_FOSR 0x0001 /* Freeze on SCSI bus reset */
117: #define M_ERRFLGS_RIN 0x0002 /* SCSI bus reset interrupt */
118: #define M_ERRFLGS_RSE 0x0004 /* Report COUGAR SCSI errors */
119: #define CIB_SBRIV 0x00002a /* scsi bus reset interrupt vector */
120: #define CIB_SOF0 0x00002c /* synchronous offset (bus 0) */
121: #define CIB_SRATE0 0x00002d /* sync negotiation rate (bus 0) */
122: #define CIB_SOF1 0x00002e /* synchronous offset (bus 0) */
123: #define CIB_SRATE1 0x00002f /* sync negotiation rate (bus 0) */
124: #define CIB_SIZE 0x000030
125:
126: /*
127: * Command Queue Entry (CQE)
128: */
129:
130: #define CQE_QECR 0x000000 /* queue entry control reg */
131: #define M_QECR_IOPB 0x0f00 /* IOPB type (must be zero) */
132: #define M_QECR_HPC 0x0004 /* High Priority command */
133: #define M_QECR_AA 0x0002 /* abort acknowledge */
134: #define M_QECR_GO 0x0001 /* Go/Busy */
135: #define CQE_IOPB_ADDR 0x000002 /* IOPB address */
136: #define CQE_CTAG 0x000004 /* command tag */
137: #define CQE_IOPB_LENGTH 0x000008 /* IOPB length */
138: #define CQE_WORK_QUEUE 0x000009 /* work queue number */
139: #define CQE_SIZE 0x00000c
140:
141: /*
142: * Command Response Block (CRB)
143: */
144:
145: #define CRB_CRSW 0x000000 /* status word */
146: #define M_CRSW_SE 0x0800 /* SCSI error (COUGAR) */
147: #define M_CRSW_RST 0x0400 /* SCSI Bus reset (COUGAR) */
148: #define M_CRSW_SC 0x0080 /* status change */
149: #define M_CRSW_CQA 0x0040 /* Command queue entry available */
150: #define M_CRSW_QMS 0x0020 /* queue mode started */
151: #define M_CRSW_AQ 0x0010 /* abort queue */
152: #define M_CRSW_EX 0x0008 /* exception */
153: #define M_CRSW_ER 0x0004 /* error */
154: #define M_CRSW_CC 0x0002 /* command complete */
155: #define M_CRSW_CRBV 0x0001 /* cmd response block valid/clear */
156: #define CRB_CTAG 0x000004 /* command tag */
157: #define CRB_IOPB_LENGTH 0x000008 /* IOPB length */
158: #define CRB_WORK_QUEUE 0x000009 /* work queue number */
159: #define CRB_SIZE 0x00000c
160:
161: /*
162: * Controller Error Vector Status Block (CEVSB)
163: * This is a variation of the CRB, _but larger_.
164: */
165:
166: #define CONTROLLER_ERROR 0x0085
167: #define NR_SCSI_ERROR 0x0885
168:
169: #define CEVSB_CRSW 0x000000 /* status word */
170: #define CEVSB_TYPE 0x000002 /* IOPB type */
171: #define CEVSB_CTAG 0x000004 /* command tag */
172: #define CEVSB_IOPB_LENGTH 0x000008 /* IOPB length */
173: #define CEVSB_WORK_QUEUE 0x000009 /* work queue number */
174: #define CEVSB_ERROR 0x00000d /* error code */
175: #define CEVSB_ERR_TYPE 0xc0 /* IOPB type error */
176: #define CEVSB_ERR_TO 0xc1 /* IOPB timeout error */
177: #define CEVSB_ERR_TR 0x82 /* Target Reconnect, no IOPB */
178: #define CEVSB_ERR_OF 0x83 /* Overflow */
179: #define CEVSB_ERR_BD 0x84 /* Bad direction */
180: #define CEVSB_ERR_NR 0x86 /* Non-Recoverabl Error */
181: #define CEVSB_ERR_PANIC 0xff /* Board Painc!!! */
182: #define CEVSB_AUXERR 0x00000e /* cougar error code */
183: #define CEVSB_SIZE 0x000010
184:
185: /*
186: * Configuration Status Block (CSB)
187: */
188:
189: #define CSB_TYPE 0x000000 /* jaguar/cougar */
190: #define COUGAR 0x4220
191: #define JAGUAR 0x0000
192: #define CSB_PCODE 0x000003 /* product code */
193: #define CSB_PVAR 0x000009 /* product variation */
194: #define CSB_FREV 0x00000d /* firmware revision level */
195: #define CSB_FDATE 0x000012 /* firmware release date */
196: #define CSB_SSIZE 0x00001a /* system memory size in KB */
197: #define CSB_BSIZE 0x00001c /* buffer memory size in KB */
198: #define CSB_PFECID 0x000020 /* primary bus FEC id */
199: #define CSB_SFECID 0x000021 /* secondary bus FEC id */
200: #define CSB_PID 0x000022 /* primary bus id */
201: #define CSB_SID 0x000023 /* secondary bus id */
202: #define CSB_LPDS 0x000024 /* last primary device selected */
203: #define CSB_LSDS 0x000025 /* last secondary device selected */
204: #define CSB_PPS 0x000026 /* primary phase sense */
205: #define CSB_SPS 0x000027 /* secondary phase sense */
206: #define CSB_DBID 0x000029 /* daughter board id */
207: #define DBID_SCSI2 0x02 /* modern SCSI ??? */
208: #define DBID_PRINTER 0x04 /* printer daughter board */
209: #define DBID_SCSI 0x06 /* SCSI daugter board */
210: #define DBID_NONE 0x07 /* no daughter board */
211: #define CSB_SDS 0x00002b /* software DIP switch */
212: #define CSB_FWQR 0x00002e /* frozen work queues register */
213: #define CSB_SIZE 0x000078
214:
215: /*
216: * IOPB Format (IOPB)
217: */
218:
219: #define IOPB_CMD 0x000000 /* command code */
220: #define IOPB_OPTION 0x000002 /* option word */
221: #define M_OPT_HEAD_TAG 0x3000 /* head of queue command queue tag */
222: #define M_OPT_ORDERED_TAG 0x2000 /* order command queue tag */
223: #define M_OPT_SIMPLE_TAG 0x1000 /* simple command queue tag */
224: #define M_OPT_GO_WIDE 0x0800 /* use WIDE transfers */
225: #define M_OPT_DIR 0x0100 /* VME direction bit */
226: #define M_OPT_SG_BLOCK 0x0008 /* scatter/gather in 512 byte blocks */
227: #define M_OPT_SS 0x0004 /* Suppress synchronous transfer */
228: #define M_OPT_SG 0x0002 /* scatter/gather bit */
229: #define M_OPT_IE 0x0001 /* Interrupt enable */
230: #define IOPB_STATUS 0x000004 /* return status word */
231: #define IOPB_NVCT 0x000008 /* normal completion vector */
232: #define IOPB_EVCT 0x000009 /* error completion vector */
233: #define IOPB_LEVEL 0x00000a /* interrupt level */
234: #define IOPB_ADDR 0x00000e /* address type and modifier */
235: #define M_ADR_TRANS 0x0c00 /* transfer type */
236: #define M_ADR_MEMT 0x0300 /* memory type */
237: #define M_ADR_MOD 0x00ff /* VME address modifier */
238: #define M_ADR_SG_LINK 0x8000 /* Scatter/Gather Link bit */
239: #define IOPB_BUFF 0x000010 /* buffer address */
240: #define IOPB_LENGTH 0x000014 /* max transfer length */
241: #define IOPB_SGTTL 0x000018 /* S/G total transfer length */
242: #define IOPB_UNIT 0x00001e /* unit address on scsi bus */
243: #define M_UNIT_EXT_LUN 0xff00 /* Extended Address */
244: #define M_UNIT_EXT 0x0080 /* Extended Address Enable */
245: #define M_UNIT_BUS 0x0040 /* SCSI Bus Selection */
246: #define M_UNIT_LUN 0x0038 /* Logical Unit Number */
247: #define M_UNIT_ID 0x0007 /* SCSI Device ID */
248: #define IOPB_SCSI_DATA 0x000020 /* SCSI words for passthrough */
249: #define IOPB_SHORT_SIZE 0x000020
250: #define IOPB_LONG_SIZE 0x000040
251:
252: /*
253: * Initialize Work Queue Command Format (WQCF)
254: * This is a specific case of IOPB.
255: */
256:
257: #define WQCF_CMD 0x000000 /* command code */
258: #define M_WOPT_IWQ 0x8000 /* initialize work queue */
259: #define M_WOPT_PE 0x0008 /* parity check enable */
260: #define M_WOPT_FE 0x0004 /* freeze on error enable */
261: #define M_WOPT_TM 0x0002 /* target mode enable */
262: #define M_WOPT_AE 0x0001 /* abort enable */
263: #define WQCF_OPTION 0x000002 /* option word */
264: #define WQCF_STATUS 0x000004 /* return status word */
265: #define WQCF_NVCT 0x000008 /* normal completion vector */
266: #define WQCF_EVCT 0x000009 /* error completion vector */
267: #define WQCF_ILVL 0x00000a /* interrupt level */
268: #define WQCF_WORKQ 0x00001c /* work queue number */
269: #define WQCF_WOPT 0x00001e /* work queue options */
270: #define WQCF_SLOTS 0x000020 /* # of slots in work queues */
271: #define WQCF_CMDTO 0x000024 /* command timeout */
272:
273: /*
274: * SCSI Reset Command Format (SRCF)
275: * This is a specific case of IOPB.
276: */
277:
278: #define SRCF_CMD 0x000000 /* command code */
279: #define SRCF_OPTION 0x000002 /* option word */
280: #define SRCF_STATUS 0x000004 /* return status word */
281: #define SRCF_NVCT 0x000008 /* normal completion vector */
282: #define SRCF_EVCT 0x000009 /* error completion vector */
283: #define SRCF_ILVL 0x00000a /* interrupt level */
284: #define SRCF_BUSID 0x00001c /* scsi bus id to reset */
285:
286: /*
287: * Device Reinitialize Command Format (DRCF)
288: * This is a specific case of IOPB.
289: */
290:
291: #define DRCF_CMD 0x000000 /* command code */
292: #define DRCF_OPTION 0x000002 /* option word */
293: #define DRCF_STATUS 0x000004 /* return status word */
294: #define DRCF_NVCT 0x000008 /* normal completion vector */
295: #define DRCF_EVCT 0x000009 /* error completion vector */
296: #define DRCF_ILVL 0x00000a /* interrupt level */
297: #define DRCF_UNIT 0x00001e /* unit address */
298:
299: /*
300: * Short I/O memory layout
301: */
302:
303: #define S_SHORTIO 0x000800
304:
305: #define sh_MCSB (0)
306: #define sh_MCE (sh_MCSB + MCSB_SIZE)
307: #define sh_CQE(x) (sh_MCE + CQE_SIZE + CQE_SIZE * (x))
308: #define sh_IOPB(x) (sh_CQE(NUM_CQE) + IOPB_LONG_SIZE * (x))
309: #define sh_MCE_IOPB (sh_IOPB(NUM_IOPB))
310: #define sh_CIB (sh_MCE_IOPB + IOPB_LONG_SIZE)
311:
312: #define sh_CSS (S_SHORTIO - CSB_SIZE)
313: #define sh_RET_IOPB (sh_CSS - IOPB_LONG_SIZE)
314: #define sh_CRB (sh_RET_IOPB - CRB_SIZE)
315: #define sh_CEVSB sh_CRB
316: #define sh_HSB (sh_CRB - HSB_SIZE)
317:
318: #if (sh_CIB + CIB_SIZE > sh_HSB)
319: #error invalid memory layout
320: #endif
321:
322: #define SELECTION_TIMEOUT 250 /* milliseconds */
323: #define VME_BUS_TIMEOUT 15 /* units of 30ms */
324: #define M328_INFINITE_TIMEOUT 0 /* wait forever */
325:
326: /*
327: * IOPB command codes
328: */
329:
330: #define IOPB_PASSTHROUGH 0x20 /* SCSI passthrough commands */
331: #define IOPB_PASSTHROUGH_EXT 0x21 /* SCSI passthrough extended */
332: #define IOPB_RESET 0x22 /* reset bus */
333:
334: #define CNTR_DIAG 0x40 /* perform diagnostics */
335: #define CNTR_INIT 0x41 /* initialize controller */
336: #define CNTR_INIT_WORKQ 0x42 /* initialize work queue */
337: #define CNTR_DUMP_INIT 0x43 /* dump initialization parameters */
338: #define CNTR_DUMP_WORDQ 0x44 /* dump work queue parameters */
339: #define CNTR_CANCEL_IOPB 0x48 /* cancel command tag */
340: #define CNTR_FLUSH_WORKQ 0x49 /* flush work queue */
341: #define CNTR_DEV_REINIT 0x4c /* reinitialize device */
342: #define CNTR_ISSUE_ABORT 0x4e /* abort has been issued */
343: #define CNTR_DOWNLOAD_FIRMWARE 0x4f /* download firmware (COUGAR) */
344:
345: #define IOPB_UNIT_VALUE(bus, target, lun) \
346: (((bus) << 6) | ((lun) << 3) | (target & 7))
347:
348: /*
349: * Memory types
350: */
351:
352: #define MEMT_16BIT 1 /* 16 bit memory type */
353: #define MEMT_32BIT 2 /* 32 bit memory type */
354: #define MEMT_SHIO 3 /* short I/O memory type */
355: #define MEMTYPE MEMT_32BIT
356:
357: /*
358: * Transfer types
359: */
360:
361: #define TT_NORMAL 0 /* normal mode transfers */
362: #define TT_BLOCK 1 /* block mode transfers */
363: #define TT_DISABLE_INC_ADDR 2 /* disable incrementing addresses */
364: #define TT_D64 3 /* D64 mode transfers */
365:
366: /*
367: * Error codes
368: */
369:
370: #define MACSI_GOOD_STATUS 0x00
371: #define MACSI_QUEUE_FULL 0x01
372: #define MACSI_CMD_CODE_ERR 0x04
373: #define MACSI_QUEUE_NUMBER_ERR 0x05
374:
375: #define RESET_BUS_STATUS 0x11 /* SCSI bus reset IOPB forced this */
376: #define NO_SECONDARY_PORT 0x12 /* second SCSI bus not available */
377: #define SCSI_DEVICE_IS_RESET 0x14
378: #define CMD_ABORT_BY_RESET 0x15
379:
380: #define VME_BUS_ERROR 0x20
381: #define VME_BUS_ACC_TIMEOUT 0x21
382: #define VME_BUS_BAD_ADDR 0x23
383: #define VME_BUS_BAD_MEM_TYPE 0x24
384: #define VME_BUS_BAD_COUNT 0x25
385: #define VME_BUS_FETCH_ERROR 0x26
386: #define VME_BUS_FETCH_TIMEOUT 0x27
387: #define VME_BUS_POST_ERROR 0x28
388: #define VME_BUS_POST_TIMEOUT 0x29
389: #define VME_BUS_BAD_FETCH_ADDR 0x2a
390: #define VME_BUS_BAD_POST_ADDR 0x2b
391: #define VME_BUS_SG_FETCH 0x2c
392: #define VME_BUS_SG_TIMEOUT 0x2d
393: #define VME_BUS_SG_COUNT 0x2e
394:
395: #define SCSI_SELECTION_TO 0x30
396: #define SCSI_DISCONNECT_TIMEOUT 0x31
397: #define SCSI_ABNORMAL_SEQ 0x32
398: #define SCSI_DISCONNECT_ERR 0x33
399: #define SCSI_XFER_EXCEPTION 0x34
400: #define SCSI_PARITY_ERROR 0x35
401:
402: #define DEVICE_NO_IOPB 0x82
403: #define IOPB_CTLR_EXH 0x83
404: #define IOPB_DIR_ERROR 0x84
405: #define COUGAR_ERROR 0x86
406: #define MACSI_INCORRECT_HW 0x90
407: #define MACSI_ILGL_IOPB_VAL 0x92
408: #define MACSI_ILLEGAL_IMAGE 0x9c
409: #define IOPB_TYPE_ERR 0xc0 /* IOPB type not 0 */
410: #define IOPB_TIMEOUT 0xc1
411:
412: #define COUGAR_PANIC 0xff
413:
414: #define MACSI_INVALID_TIMEOUT 0x843
415:
416: /*
417: * VME addressing modes
418: */
419:
420: #define ADRM_STD_S_P 0x3e /* standard supervisory program */
421: #define ADRM_STD_S_D 0x3d /* standard supervisory data */
422: #define ADRM_STD_N_P 0x3a /* standard normal program */
423: #define ADRM_STD_N_D 0x39 /* standard normal data */
424: #define ADRM_SHT_S_IO 0x2d /* short supervisory I/O */
425: #define ADRM_SHT_N_IO 0x29 /* short normal I/O */
426: #define ADRM_EXT_S_P 0x0e /* extended supervisory program */
427: #define ADRM_EXT_S_D 0x0d /* extended supervisory data */
428: #define ADRM_EXT_N_P 0x0a /* extended normal program */
429: #define ADRM_EXT_N_D 0x09 /* extended normal data */
430: #define ADRM_EXT_S_BM 0x0f /* extended supervisory block mode */
431: #define ADRM_EXT_S_D64 0x0c /* extended supervisory D64 mode */
432:
433: #define ADDR_MOD ((TT_NORMAL << 10) | (MEMTYPE << 8) | ADRM_EXT_S_D)
434: #define BLOCK_MOD ((TT_BLOCK << 10) | (MEMTYPE << 8) | ADRM_EXT_S_BM)
435: #define D64_MOD ((TT_D64 << 10) | (MEMTYPE << 8) | ADRM_EXT_S_D64)
436: #define SHIO_MOD ((TT_NORMAL << 10) | (MEMT_SHIO << 8) | ADRM_SHT_N_IO)
437:
438: #endif /* _MVME328_REG_H_ */
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