Annotation of sys/arch/mvme88k/dev/if_lereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_lereg.h,v 1.6 2007/05/25 21:27:15 krw Exp $ */
2:
3: /*-
4: * Copyright (c) 1982, 1992, 1993
5: * The Regents of the University of California. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. Neither the name of the University nor the names of its contributors
16: * may be used to endorse or promote products derived from this software
17: * without specific prior written permission.
18: *
19: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29: * SUCH DAMAGE.
30: *
31: * @(#)if_lereg.h 8.2 (Berkeley) 10/30/93
32: */
33:
34: #define VLEMEMSIZE 0x00040000
35: #define VLEMEMBASE 0xfd6c0000
36:
37: /*
38: * LANCE registers for MVME376
39: */
40: struct vlereg1 {
41: volatile u_int16_t ler1_csr; /* board control/status register */
42: volatile u_int16_t ler1_vec; /* interrupt vector register */
43: volatile u_int16_t ler1_rdp; /* data port */
44: volatile u_int16_t ler1_rap; /* register select port */
45: volatile u_int16_t ler1_ear; /* ethernet address register */
46: };
47:
48: #define NVRAM_EN 0x0008 /* NVRAM enable bit (active low) */
49: #define INTR_EN 0x0010 /* interrupt enable bit (active low) */
50: #define PARITYB 0x0020 /* parity error clear bit */
51: #define HW_RS 0x0040 /* hardware reset bit (active low) */
52: #define SYSFAILB 0x0080 /* SYSFAIL bit */
53:
54: #define NVRAM_RWEL 0xe0 /* Reset write enable latch */
55: #define NVRAM_STO 0x60 /* Store ram to eeprom */
56: #define NVRAM_SLP 0xa0 /* Novram into low power mode */
57: #define NVRAM_WRITE 0x20 /* Writes word from location x */
58: #define NVRAM_SWEL 0xc0 /* Set write enable latch */
59: #define NVRAM_RCL 0x40 /* Recall eeprom data into ram */
60: #define NVRAM_READ 0x00 /* Reads word from location x */
61:
62: #define CDELAY delay(10000)
63: #define WRITE_CSR_OR(x) \
64: do { \
65: ((struct le_softc *)sc)->sc_csr |= (x); \
66: reg1->ler1_csr = ((struct le_softc *)sc)->sc_csr; \
67: } while (0)
68: #define WRITE_CSR_AND(x) \
69: do { \
70: ((struct le_softc *)sc)->sc_csr &= ~(x); \
71: reg1->ler1_csr = ((struct le_softc *)sc)->sc_csr; \
72: } while (0)
73: #define ENABLE_NVRAM WRITE_CSR_AND(NVRAM_EN)
74: #define DISABLE_NVRAM WRITE_CSR_OR(NVRAM_EN)
75: #define ENABLE_INTR WRITE_CSR_AND(INTR_EN)
76: #define DISABLE_INTR WRITE_CSR_OR(INTR_EN)
77: #define RESET_HW \
78: do { \
79: WRITE_CSR_AND(HW_RS); \
80: CDELAY; \
81: } while (0)
82: #define SET_VEC(x) \
83: reg1->ler1_vec = (x)
84: #define SYSFAIL_CL WRITE_CSR_AND(SYSFAILB)
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