Annotation of sys/arch/mvme88k/dev/clreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: clreg.h,v 1.6 2004/04/24 19:51:47 miod Exp $ */
2:
3: /* Copyright (c) 1998 Steve Murphree, Jr.
4: * Copyright (c) 1995 Dale Rahn. All rights reserved.
5: *
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. The name of the author may not be used to endorse or promote products
16: * derived from this software without specific prior written permission.
17: *
18: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28: */
29:
30: #define CL_COR7 0x0007
31: #define CL_LIVR 0x0009
32: #define CL_COR1 0x0010
33: #define CL_IER 0x0011
34: #define CL_STCR 0x0012
35: #define CL_CCR 0x0013
36: #define CL_COR5 0x0014
37: #define CL_COR4 0x0015
38: #define CL_COR3 0x0016
39: #define CL_COR2 0x0017
40: #define CL_COR6 0x0018
41: #define CL_DMABSTS 0x0019
42: #define CL_CSR 0x001a
43: #define CL_CMR 0x001b
44: #define CL_SCHR4 0x001c
45: #define CL_SCHR3 0x001d
46: #define CL_SCHR2 0x001e
47: #define CL_SCHR1 0x001f
48: #define CL_SCRH 0x0022
49: #define CL_SCRL 0x0023
50:
51: #define CL_RTPR 0x0024
52: #define CL_RTPRH 0x0024
53: #define CL_RTPRL 0x0025
54:
55: #define CL_LICR 0x0026
56: #define CL_LNXT 0x002e
57: #define CL_RFOC 0x0030
58:
59: #define CL_TCBADRU 0x0038
60: #define CL_TCBADRL 0x003a
61: #define CL_RCBADRU 0x003c
62: #define CL_RCBADRL 0x003e
63: #define CL_ARBADRU 0x0040
64: #define CL_ARBARDL 0x0042
65: #define CL_BRBADRU 0x0044
66: #define CL_BRBADRL 0x0046
67: #define CL_BRBCNT 0x0048
68: #define CL_ARBCNT 0x004a
69:
70: #define CL_BRBSTS 0x004e
71: #define CL_ARBSTS 0x004f
72:
73: #define CL_ATBADR 0x0050
74: #define CL_ATBADRU 0x0050
75: #define CL_ATBADRL 0x0052
76: #define CL_BTBADR 0x0054
77: #define CL_BTBADRU 0x0054
78: #define CL_BTBADRL 0x0056
79:
80: #define CL_BTBCNT 0x0058
81: #define CL_ATBCNT 0x005a
82:
83: #define CL_BTBSTS 0x005e
84: #define CL_ATBSTS 0x005f
85:
86: #define CL_TFTC 0x0080
87: #define CL_GFRCR 0x0081
88: #define CL_REOIR 0x0084
89: #define CL_TEOIR 0x0085
90: #define CL_MEOIR 0x0086
91:
92: #define CL_RISR 0x0088
93: #define CL_RISRH 0x0088
94: #define CL_RISRL 0x0089
95:
96: #define CL_TISR 0x008a
97: #define CL_MISR 0x008b
98: #define CL_BERCNT 0x008e
99: #define CL_TCOR 0x00c0
100: #define CL_TBPR 0x00c3
101: #define CL_RCOR 0x00c8
102: #define CL_RBPR 0x00cb
103: #define CL_CPSR 0x00d6
104: #define CL_TPR 0x00da
105: #define CL_MSVR_RTS 0x00de
106: #define CL_MSVR_DTR 0x00df
107: #define CL_TPILR 0x00e0
108: #define CL_RPILR 0x00e1
109: #define CL_STK 0x00e2
110: #define CL_MPILR 0x00e3
111: #define CL_TIR 0x00ec
112: #define CL_RIR 0x00ed
113: #define CL_CAR 0x00ee
114: #define CL_MIR 0x00ef
115: #define CL_DMR 0x00f6
116: #define CL_RDR 0x00f8
117: #define CL_TDR 0x00f8
118:
119: #define CD2400_SIZE 0x200
120:
121: /*
122: * Cirrus chip base address on the mvme1x7 boards.
123: */
124: #define CD2400_BASE_ADDR 0xfff45000
125: #define CD2400_SECONDARY_ADDR 0xfff45200
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