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File: [local] / sys / arch / mvme88k / dev / busswreg.h (download)
Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:04:37 2008 UTC (16 years, 5 months ago) by nbrk
Import of OpenBSD 4.2 release kernel tree with initial code to support Jornada 720/728, StrongARM 1110-based handheld PC. At this point kernel roots on NFS and boots into vfs_mountroot() and traps. What is supported: - glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode (needs some palette tweaks for non black/white/blue colors, i think) - saic, SA11x0 interrupt controller (needs cleanup) - sacom, SA11x0 UART (supported only as boot console for now) - SA11x0 GPIO controller fully supported (but can't handle multiple interrupt handlers on one gpio pin) - sassp, SSP port on SA11x0 that attaches spibus - Jornada microcontroller (jmcu) to control kbd, battery, etc throught the SPI bus (wskbd attaches on jmcu, but not tested) - tod functions seem work - initial code for SA-1111 (chip companion) : this is TODO Next important steps, i think: - gpio and intc on sa1111 - pcmcia support for sa11x0 (and sa1111 help logic) - REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs) - root on wd0! (using already supported PCMCIA-ATA) |
/* $OpenBSD: busswreg.h,v 1.7 2005/12/11 21:31:36 miod Exp $ */ /* * Memory map for BusSwitch chip found in mvme197 boards. */ #ifndef BUSSWREG_H #define BUSSWREG_H #define BS_BASE 0xfff00000 #define BS_SIZE 0x00000120 #define BS_CHIPID 0x0000 #define BS_CHIPREV 0x0001 #define BS_GCSR 0x0002 #define BS_IODATA 0x0004 #define BS_IODIR 0x0006 #define BS_PSAR1 0x0008 #define BS_PEAR1 0x000a #define BS_PSAR2 0x000c #define BS_PEAR2 0x000e #define BS_PSAR3 0x0010 #define BS_PEAR3 0x0012 #define BS_PSAR4 0x0014 #define BS_PEAR4 0x0016 #define BS_PTR1 0x0018 #define BS_PTSR1 0x001a #define BS_PTR2 0x001c #define BS_PTSR2 0x001e #define BS_PTR3 0x0020 #define BS_PTSR3 0x0022 #define BS_PTR4 0x0024 #define BS_PTSR4 0x0026 #define BS_SSAR1 0x0028 #define BS_SEAR1 0x002a #define BS_SSAR2 0x002c #define BS_SEAR2 0x002e #define BS_SSAR3 0x0030 #define BS_SEAR3 0x0032 #define BS_SSAR4 0x0034 #define BS_SEAR4 0x0036 #define BS_STR1 0x0038 #define BS_STSR1 0x003a #define BS_STR2 0x003c #define BS_STSR2 0x003e #define BS_STR3 0x0040 #define BS_STSR3 0x0042 #define BS_STR4 0x0044 #define BS_STSR4 0x0046 #define BS_PAR 0x0048 #define BS_SAR 0x004c #define BS_BTIMER 0x0051 #define BS_PADJUST 0x0052 #define BS_PCOUNT 0x0053 #define BS_PAL 0x0054 #define BS_WPPA 0x0058 #define BS_WPTPA 0x005c #define BS_WPPAT 0x005e #define BS_ROMCR 0x0060 #define BS_TCTRL1 0x0062 #define BS_TCTRL2 0x0063 #define BS_LEVEL 0x0064 #define BS_MASK 0x0065 #define BS_ISEL0 0x0066 #define BS_ISEL1 0x0067 #define BS_ABORT 0x0068 #define BS_CPINT 0x0069 #define BS_TINT1 0x006a #define BS_TINT2 0x006b #define BS_WPINT 0x006c #define BS_PALINT 0x006d #define BS_XINT 0x006e #define BS_VBASE 0x006f #define BS_TCOMP1 0x0070 #define BS_TCOUNT1 0x0074 #define BS_TCOMP2 0x0078 #define BS_TCOUNT2 0x007c #define BS_GPR 0x0080 #define BS_XCTAGS 0x0090 #define BS_XCCR 0x0100 #define BS_VEC 0x0104 #define BUSSWITCH_ID 0x21 /* value at CHIPID */ /* GCSR bit definitions */ #define BS_GCSR_APRI0 0x0001 /* Bus Request 0 Priority indicator (CPU0)*/ #define BS_GCSR_APRI1 0x0002 /* Bus Request 1 Priority indicator (CPU1)*/ #define BS_GCSR_APRI2 0x0003 /* Bus Request 2 Priority indicator (mc88410)*/ #define BS_GCSR_AMOD 0x0004 /* Arbitration Mode */ #define BS_GCSR_BREN 0x0008 /* Bus Request Enable */ #define BS_GCSR_CPUID 0x0010 /* CPU ID */ #define BS_GCSR_B410 0x0020 /* BUS410 indicator */ #define BS_GCSR_INVD 0x0040 /* Invalidate Decoder */ #define BS_GCSR_USR 0x0080 /* User Access Enable */ #define BS_GCSR_XIPL 0x0100 /* External IPL Enable */ #define BS_GCSR_TCPU1 0x0200 /* Test CPU 1 Registers */ #define BS_GCSR_XCC 0x0400 /* External Cache Controller */ #define BS_GCSR_INCB 0x0800 /* Increment On Burst */ #define BS_GCSR_TDPR 0x2000 /* Test Dual Processor Registers */ #define BS_GCSR_TBB 0x4000 /* Test Bus Busy */ #define BS_GCSR_POR 0x8000 /* Power On Reset */ /* System Attribute Registers bit definitions */ #define BS_SAR_DEN 0x01 /* Decode Enable */ #define BS_SAR_INVR 0x04 /* Invalidate On Reads */ #define BS_SAR_GBL 0x08 /* Global Access */ /* Bus Timer Register bit definitions */ #define BS_BTIMER_PBT8 0x00 /* Processor Bus Timout, 8 usec */ #define BS_BTIMER_PBT64 0x01 /* Processor Bus Timout, 64 usec */ #define BS_BTIMER_PBT256 0x02 /* Processor Bus Timout, 256 usec */ #define BS_BTIMER_PBTD 0x03 /* Processor Bus Timout, disable */ #define BS_BTIMER_SBT8 (0x00 << 2) /* System Bus Timout, 8 usec */ #define BS_BTIMER_SBT64 (0x01 << 2) /* System Bus Timout, 64 usec */ #define BS_BTIMER_SBT256 (0x02 << 2) /* System Bus Timout, 256 usec */ #define BS_BTIMER_SBTD (0x03 << 2) /* System Bus Timout, disable */ /* Prescaler Adjust values */ #define BS_PADJUST_50 0xce /* 50 MHz clock */ #define BS_PADJUST_40 0xd8 /* 40 MHz clock */ #define BS_PADJUST_33 0xdf /* 33 MHz clock */ #define BS_PADJUST_25 0xe7 /* 25 MHz clock */ /* ROM Control Register bit definitions */ #define BS_ROMCR_WEN0 0x0100 #define BS_ROMCR_WEN1 0x0200 #define BS_ROMCR_SGLB 0x0400 #define BS_ROMCR_ROM0 0x8000 /* External Cache Control Register bit definitions */ #define BS_XCC_F0 0x00000001 #define BS_XCC_F1 0x00000002 #define BS_XCC_FBSY 0x00000004 #define BS_XCC_DIAG 0x00000008 /* Abort Control Register */ #define BS_ABORT_ICLR 0x08 /* abort interrupt clear */ #define BS_ABORT_IEN 0x10 /* abort interrupt enable */ #define BS_ABORT_INT 0x20 /* abort interrupt received */ #define BS_ABORT_ABT 0x40 /* abort interrupt asserted */ /* Cross Processor Interrupt Register */ #define BS_CPI_ICLR 0x08 /* cpi interrupt clear */ #define BS_CPI_IEN 0x10 /* cpi interrupt enable */ #define BS_CPI_INT 0x20 /* cpi interrupt received */ #define BS_CPI_STAT 0x40 /* cpi interrupt status */ #define BS_CPI_SCPI 0x80 /* send cross proc interrupt */ /* Timer Interrupt 1 Register */ #define BS_TINT1_ICLR 0x08 /* timer 1 interrupt clear */ #define BS_TINT1_IEN 0x10 /* timer 1 interrupt enable */ #define BS_TINT1_INT 0x20 /* timer 1 interrupt received */ #define BS_TINT1_LM 0x07 /* timer 1 level mask */ #define BS_TINT1_LEVEL(x) (x & BS_TINT1_LM) /* Timer Interrupt 2 Register */ #define BS_TINT2_ICLR 0x08 /* timer 1 interrupt clear */ #define BS_TINT2_IEN 0x10 /* timer 1 interrupt enable */ #define BS_TINT2_INT 0x20 /* timer 1 interrupt received */ #define BS_TINT2_LM 0x07 /* timer 1 level mask */ #define BS_TINT2_LEVEL(x) (x & BS_TINT2_LM) /* Write Post Control Register */ #define BS_WPINT_ICLR 0x08 /* WPINT interrupt clear */ #define BS_WPINT_IEN 0x10 /* WPINT interrupt enable */ #define BS_WPINT_INT 0x20 /* WPINT interrupt received */ #define BS_WPINT_LM 0x07 /* WPINT level mask */ #define BS_WPINT_LEVEL(x) (x & BS_WPINT_LM) /* Processor Address Log Interrupt Register */ #define BS_PALINT_ICLR 0x00 /* PALINT interrupt clear */ #define BS_PALINT_IEN 0x10 /* PALINT interrupt enable */ #define BS_PALINT_INT 0x20 /* PALINT interrupt received */ #define BS_PALINT_PLTY 0x80 /* PALINT polarity */ #define BS_PALINT_LM 0x07 /* PALINT level mask */ #define BS_PALINT_LEVEL(x) (x & BS_PALINT_LM) /* External Interrupt Register */ #define BS_XINT_ICLR 0x00 /* XINT interrupt clear */ #define BS_XINT_IEN 0x10 /* XINT interrupt enable */ #define BS_XINT_INT 0x20 /* XINT interrupt received */ #define BS_XINT_EL 0x40 /* XINT edge/level */ #define BS_XINT_PLTY 0x80 /* XINT polarity */ #define BS_XINT_LM 0x07 /* XINT level mask */ #define BS_XINT_LEVEL(x) (x & BS_XINT_LM) /* Vector Base Register (A read upon an interrupt reveals the source) */ #define BS_VBASE_SRC_TMR1 0x0 #define BS_VBASE_SRC_TMR2 0x1 #define BS_VBASE_SRC_WPE 0x2 #define BS_VBASE_SRC_PAL 0x3 #define BS_VBASE_SRC_EXT 0x4 /* external interrupt */ #define BS_VBASE_SRC_SPUR 0x7 /* spurious interrupt */ /* We lock off BusSwitch vectors at 0x40 */ #define BS_VECBASE 0x40 #define BS_NVEC 0x10 /* Bottom 4 bits of the vector returned during IACK cycle */ #define BS_TMR1IRQ 0x01 /* lowest */ #define BS_TMR2IRQ 0x02 #define BS_ABORTIRQ 0x03 /* Define the Abort vector */ #define BS_ABORTVEC (BS_VECBASE | BS_ABORTIRQ) #endif /* BUSSWREG_H */