Annotation of sys/arch/mvme88k/dev/busswreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: busswreg.h,v 1.7 2005/12/11 21:31:36 miod Exp $ */
2:
3: /*
4: * Memory map for BusSwitch chip found in mvme197 boards.
5: */
6: #ifndef BUSSWREG_H
7: #define BUSSWREG_H
8:
9: #define BS_BASE 0xfff00000
10: #define BS_SIZE 0x00000120
11:
12: #define BS_CHIPID 0x0000
13: #define BS_CHIPREV 0x0001
14: #define BS_GCSR 0x0002
15: #define BS_IODATA 0x0004
16: #define BS_IODIR 0x0006
17: #define BS_PSAR1 0x0008
18: #define BS_PEAR1 0x000a
19: #define BS_PSAR2 0x000c
20: #define BS_PEAR2 0x000e
21: #define BS_PSAR3 0x0010
22: #define BS_PEAR3 0x0012
23: #define BS_PSAR4 0x0014
24: #define BS_PEAR4 0x0016
25: #define BS_PTR1 0x0018
26: #define BS_PTSR1 0x001a
27: #define BS_PTR2 0x001c
28: #define BS_PTSR2 0x001e
29: #define BS_PTR3 0x0020
30: #define BS_PTSR3 0x0022
31: #define BS_PTR4 0x0024
32: #define BS_PTSR4 0x0026
33: #define BS_SSAR1 0x0028
34: #define BS_SEAR1 0x002a
35: #define BS_SSAR2 0x002c
36: #define BS_SEAR2 0x002e
37: #define BS_SSAR3 0x0030
38: #define BS_SEAR3 0x0032
39: #define BS_SSAR4 0x0034
40: #define BS_SEAR4 0x0036
41: #define BS_STR1 0x0038
42: #define BS_STSR1 0x003a
43: #define BS_STR2 0x003c
44: #define BS_STSR2 0x003e
45: #define BS_STR3 0x0040
46: #define BS_STSR3 0x0042
47: #define BS_STR4 0x0044
48: #define BS_STSR4 0x0046
49: #define BS_PAR 0x0048
50: #define BS_SAR 0x004c
51: #define BS_BTIMER 0x0051
52: #define BS_PADJUST 0x0052
53: #define BS_PCOUNT 0x0053
54: #define BS_PAL 0x0054
55: #define BS_WPPA 0x0058
56: #define BS_WPTPA 0x005c
57: #define BS_WPPAT 0x005e
58: #define BS_ROMCR 0x0060
59: #define BS_TCTRL1 0x0062
60: #define BS_TCTRL2 0x0063
61: #define BS_LEVEL 0x0064
62: #define BS_MASK 0x0065
63: #define BS_ISEL0 0x0066
64: #define BS_ISEL1 0x0067
65: #define BS_ABORT 0x0068
66: #define BS_CPINT 0x0069
67: #define BS_TINT1 0x006a
68: #define BS_TINT2 0x006b
69: #define BS_WPINT 0x006c
70: #define BS_PALINT 0x006d
71: #define BS_XINT 0x006e
72: #define BS_VBASE 0x006f
73: #define BS_TCOMP1 0x0070
74: #define BS_TCOUNT1 0x0074
75: #define BS_TCOMP2 0x0078
76: #define BS_TCOUNT2 0x007c
77: #define BS_GPR 0x0080
78: #define BS_XCTAGS 0x0090
79: #define BS_XCCR 0x0100
80: #define BS_VEC 0x0104
81:
82: #define BUSSWITCH_ID 0x21 /* value at CHIPID */
83:
84: /* GCSR bit definitions */
85: #define BS_GCSR_APRI0 0x0001 /* Bus Request 0 Priority indicator (CPU0)*/
86: #define BS_GCSR_APRI1 0x0002 /* Bus Request 1 Priority indicator (CPU1)*/
87: #define BS_GCSR_APRI2 0x0003 /* Bus Request 2 Priority indicator (mc88410)*/
88: #define BS_GCSR_AMOD 0x0004 /* Arbitration Mode */
89: #define BS_GCSR_BREN 0x0008 /* Bus Request Enable */
90: #define BS_GCSR_CPUID 0x0010 /* CPU ID */
91: #define BS_GCSR_B410 0x0020 /* BUS410 indicator */
92: #define BS_GCSR_INVD 0x0040 /* Invalidate Decoder */
93: #define BS_GCSR_USR 0x0080 /* User Access Enable */
94: #define BS_GCSR_XIPL 0x0100 /* External IPL Enable */
95: #define BS_GCSR_TCPU1 0x0200 /* Test CPU 1 Registers */
96: #define BS_GCSR_XCC 0x0400 /* External Cache Controller */
97: #define BS_GCSR_INCB 0x0800 /* Increment On Burst */
98: #define BS_GCSR_TDPR 0x2000 /* Test Dual Processor Registers */
99: #define BS_GCSR_TBB 0x4000 /* Test Bus Busy */
100: #define BS_GCSR_POR 0x8000 /* Power On Reset */
101:
102: /* System Attribute Registers bit definitions */
103: #define BS_SAR_DEN 0x01 /* Decode Enable */
104: #define BS_SAR_INVR 0x04 /* Invalidate On Reads */
105: #define BS_SAR_GBL 0x08 /* Global Access */
106:
107: /* Bus Timer Register bit definitions */
108: #define BS_BTIMER_PBT8 0x00 /* Processor Bus Timout, 8 usec */
109: #define BS_BTIMER_PBT64 0x01 /* Processor Bus Timout, 64 usec */
110: #define BS_BTIMER_PBT256 0x02 /* Processor Bus Timout, 256 usec */
111: #define BS_BTIMER_PBTD 0x03 /* Processor Bus Timout, disable */
112: #define BS_BTIMER_SBT8 (0x00 << 2) /* System Bus Timout, 8 usec */
113: #define BS_BTIMER_SBT64 (0x01 << 2) /* System Bus Timout, 64 usec */
114: #define BS_BTIMER_SBT256 (0x02 << 2) /* System Bus Timout, 256 usec */
115: #define BS_BTIMER_SBTD (0x03 << 2) /* System Bus Timout, disable */
116:
117: /* Prescaler Adjust values */
118: #define BS_PADJUST_50 0xce /* 50 MHz clock */
119: #define BS_PADJUST_40 0xd8 /* 40 MHz clock */
120: #define BS_PADJUST_33 0xdf /* 33 MHz clock */
121: #define BS_PADJUST_25 0xe7 /* 25 MHz clock */
122:
123: /* ROM Control Register bit definitions */
124: #define BS_ROMCR_WEN0 0x0100
125: #define BS_ROMCR_WEN1 0x0200
126: #define BS_ROMCR_SGLB 0x0400
127: #define BS_ROMCR_ROM0 0x8000
128:
129: /* External Cache Control Register bit definitions */
130: #define BS_XCC_F0 0x00000001
131: #define BS_XCC_F1 0x00000002
132: #define BS_XCC_FBSY 0x00000004
133: #define BS_XCC_DIAG 0x00000008
134:
135: /* Abort Control Register */
136: #define BS_ABORT_ICLR 0x08 /* abort interrupt clear */
137: #define BS_ABORT_IEN 0x10 /* abort interrupt enable */
138: #define BS_ABORT_INT 0x20 /* abort interrupt received */
139: #define BS_ABORT_ABT 0x40 /* abort interrupt asserted */
140:
141: /* Cross Processor Interrupt Register */
142: #define BS_CPI_ICLR 0x08 /* cpi interrupt clear */
143: #define BS_CPI_IEN 0x10 /* cpi interrupt enable */
144: #define BS_CPI_INT 0x20 /* cpi interrupt received */
145: #define BS_CPI_STAT 0x40 /* cpi interrupt status */
146: #define BS_CPI_SCPI 0x80 /* send cross proc interrupt */
147:
148: /* Timer Interrupt 1 Register */
149: #define BS_TINT1_ICLR 0x08 /* timer 1 interrupt clear */
150: #define BS_TINT1_IEN 0x10 /* timer 1 interrupt enable */
151: #define BS_TINT1_INT 0x20 /* timer 1 interrupt received */
152: #define BS_TINT1_LM 0x07 /* timer 1 level mask */
153: #define BS_TINT1_LEVEL(x) (x & BS_TINT1_LM)
154:
155: /* Timer Interrupt 2 Register */
156: #define BS_TINT2_ICLR 0x08 /* timer 1 interrupt clear */
157: #define BS_TINT2_IEN 0x10 /* timer 1 interrupt enable */
158: #define BS_TINT2_INT 0x20 /* timer 1 interrupt received */
159: #define BS_TINT2_LM 0x07 /* timer 1 level mask */
160: #define BS_TINT2_LEVEL(x) (x & BS_TINT2_LM)
161:
162: /* Write Post Control Register */
163: #define BS_WPINT_ICLR 0x08 /* WPINT interrupt clear */
164: #define BS_WPINT_IEN 0x10 /* WPINT interrupt enable */
165: #define BS_WPINT_INT 0x20 /* WPINT interrupt received */
166: #define BS_WPINT_LM 0x07 /* WPINT level mask */
167: #define BS_WPINT_LEVEL(x) (x & BS_WPINT_LM)
168:
169: /* Processor Address Log Interrupt Register */
170: #define BS_PALINT_ICLR 0x00 /* PALINT interrupt clear */
171: #define BS_PALINT_IEN 0x10 /* PALINT interrupt enable */
172: #define BS_PALINT_INT 0x20 /* PALINT interrupt received */
173: #define BS_PALINT_PLTY 0x80 /* PALINT polarity */
174: #define BS_PALINT_LM 0x07 /* PALINT level mask */
175: #define BS_PALINT_LEVEL(x) (x & BS_PALINT_LM)
176:
177: /* External Interrupt Register */
178: #define BS_XINT_ICLR 0x00 /* XINT interrupt clear */
179: #define BS_XINT_IEN 0x10 /* XINT interrupt enable */
180: #define BS_XINT_INT 0x20 /* XINT interrupt received */
181: #define BS_XINT_EL 0x40 /* XINT edge/level */
182: #define BS_XINT_PLTY 0x80 /* XINT polarity */
183: #define BS_XINT_LM 0x07 /* XINT level mask */
184: #define BS_XINT_LEVEL(x) (x & BS_XINT_LM)
185:
186: /* Vector Base Register (A read upon an interrupt reveals the source) */
187: #define BS_VBASE_SRC_TMR1 0x0
188: #define BS_VBASE_SRC_TMR2 0x1
189: #define BS_VBASE_SRC_WPE 0x2
190: #define BS_VBASE_SRC_PAL 0x3
191: #define BS_VBASE_SRC_EXT 0x4 /* external interrupt */
192: #define BS_VBASE_SRC_SPUR 0x7 /* spurious interrupt */
193:
194: /* We lock off BusSwitch vectors at 0x40 */
195: #define BS_VECBASE 0x40
196: #define BS_NVEC 0x10
197:
198: /* Bottom 4 bits of the vector returned during IACK cycle */
199: #define BS_TMR1IRQ 0x01 /* lowest */
200: #define BS_TMR2IRQ 0x02
201: #define BS_ABORTIRQ 0x03
202:
203: /* Define the Abort vector */
204: #define BS_ABORTVEC (BS_VECBASE | BS_ABORTIRQ)
205:
206: #endif /* BUSSWREG_H */
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