Annotation of sys/arch/mvme68k/dev/wdscreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: wdscreg.h,v 1.2 2003/06/02 23:27:50 millert Exp $ */
2:
3: /*
4: * Copyright (c) 1994 Christian E. Hopps
5: * Copyright (c) 1982, 1990 The Regents of the University of California.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. Neither the name of the University nor the names of its contributors
17: * may be used to endorse or promote products derived from this software
18: * without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30: * SUCH DAMAGE.
31: *
32: * @(#)dmareg.h
33: */
34: #ifndef _MVME68K_DEV_WDSCREG_H_
35: #define _MVME68K_DEV_WDSCREG_H_
36:
37: #define DMAC_CSR_ENABLE (1 << 0) /* Enable the DMAC */
38: #define DMAC_CSR_TABLE (1 << 1) /* Select Table Mode */
39: #define DMAC_CSR_WRITE (1 << 2) /* Write data from RAM to SCSI */
40: #define DMAC_CSR_TBUSERR (1 << 3) /* Bus error during table walk */
41: #define DMAC_CSR_DBUSERR (1 << 4) /* Bus error during data xfer */
42: #define DMAC_CSR_TSIZE (1 << 5) /* Table addr. not in 32 bits */
43: #define DMAC_CSR_8BITS (1 << 6) /* Non-8 bit handshake */
44: #define DMAC_CSR_DONE (1 << 7) /* Transfer complete, or error */
45:
46: #define DMAC_SR_HOLDING 0x0f /* Data holding state */
47: #define DMAC_SR_INCREMENT 0xf0 /* Increment value */
48:
49: #endif
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