Annotation of sys/arch/mvme68k/dev/vsreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: vsreg.h,v 1.7 2006/12/21 02:28:47 krw Exp $ */
! 2: /*
! 3: * Copyright (c) 1999 Steve Murphree, Jr.
! 4: * Copyright (c) 1990 The Regents of the University of California.
! 5: * All rights reserved.
! 6: *
! 7: * This code is derived from source contributed by Mark Bellon.
! 8: *
! 9: * Redistribution and use in source and binary forms, with or without
! 10: * modification, are permitted provided that the following conditions
! 11: * are met:
! 12: * 1. Redistributions of source code must retain the above copyright
! 13: * notice, this list of conditions and the following disclaimer.
! 14: * 2. Redistributions in binary form must reproduce the above copyright
! 15: * notice, this list of conditions and the following disclaimer in the
! 16: * documentation and/or other materials provided with the distribution.
! 17: * 3. Neither the name of the University nor the names of its contributors
! 18: * may be used to endorse or promote products derived from this software
! 19: * without specific prior written permission.
! 20: *
! 21: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 24: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 25: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 31: * SUCH DAMAGE.
! 32: */
! 33:
! 34: #if !defined(_M328REG_H_)
! 35: #define _M328REG_H_
! 36:
! 37:
! 38: typedef struct LONGV
! 39: {
! 40: u_short msw;
! 41: u_short lsw;
! 42: } LONGV;
! 43:
! 44: #define MSW(x) ((x).msw)
! 45: #define LSW(x) ((x).lsw)
! 46:
! 47: /*
! 48: * macro to convert a unsigned long to a LONGV
! 49: */
! 50:
! 51: #define LV( a, b) \
! 52: { \
! 53: MSW( a ) = ( (( (unsigned long)(b) ) >> 16) & 0xffff ); \
! 54: LSW( a ) = ( ( (unsigned long)(b) ) & 0xffff); \
! 55: }
! 56:
! 57: /*
! 58: * macro to convert a LONGV to a unsigned long
! 59: */
! 60:
! 61: #define VL( a, b) \
! 62: { \
! 63: a = ( (((unsigned long) MSW(b)) << 16 ) | (((unsigned long) LSW(b)) & 0x0ffff) ); \
! 64: }
! 65:
! 66: #define COUGAR 0x4220 /* board type (config. status area) */
! 67: #define JAGUAR 0
! 68:
! 69: /*
! 70: * JAGUAR specific device limits.
! 71: */
! 72:
! 73: #define JAGUAR_MIN_Q_SIZ 2 /* got'a have at least one! */
! 74: #define JAGUAR_MAX_Q_SIZ 2 /* can't have more */
! 75: #define JAGUAR_MAX_CTLR_CMDS 80 /* Interphase says so */
! 76:
! 77: /*
! 78: * COUGAR specific device limits.
! 79: */
! 80:
! 81: #define COUGAR_MIN_Q_SIZ 2 /* got'a have at least one! */
! 82: #define COUGAR_CMDS_PER_256K 42 /* Interphase says so */
! 83:
! 84: /*
! 85: * Structures
! 86: */
! 87:
! 88: #define NUM_CQE 10
! 89: #define MAX_IOPB 64
! 90: #define NUM_IOPB NUM_CQE
! 91: #define S_IOPB_RES (MAX_IOPB - sizeof(M328_short_IOPB))
! 92: #define S_SHORTIO 2048
! 93: #define S_IOPB sizeof(M328_IOPB)
! 94: #define S_CIB sizeof(M328_CIB)
! 95: #define S_MCSB sizeof(M328_MCSB)
! 96: #define S_MCE sizeof(M328_CQE)
! 97: #define S_CQE (sizeof(M328_CQE) * NUM_CQE)
! 98: #define S_HIOPB (sizeof(M328_IOPB) * NUM_IOPB)
! 99: #define S_HSB sizeof(M328_HSB)
! 100: #define S_CRB sizeof(M328_CRB)
! 101: #define S_CSS sizeof(M328_CSB)
! 102: #define S_NOT_HOST (S_MCSB + S_MCE + S_CQE + S_HIOPB + S_IOPB + \
! 103: S_CIB + S_HSB + S_CRB + S_IOPB + S_CSS)
! 104: #define S_HUS_FREE (S_SHORTIO - S_NOT_HOST)
! 105:
! 106: #define S_WQCF sizeof(M328_WQCF)
! 107:
! 108: #define HOST_ID 0x4321
! 109:
! 110:
! 111: /**************** Master Control Status Block (MCSB) *******************/
! 112:
! 113: /*
! 114: * defines for Master Status Register
! 115: */
! 116:
! 117: #define M_MSR_QFC 0x0004 /* queue flush complete */
! 118: #define M_MSR_BOK 0x0002 /* board OK */
! 119: #define M_MSR_CNA 0x0001 /* controller not available */
! 120:
! 121: /*
! 122: * defines for Master Control Register
! 123: */
! 124:
! 125: #define M_MCR_SFEN 0x2000 /* sysfail enable */
! 126: #define M_MCR_RES 0x1000 /* reset controller */
! 127: #define M_MCR_FLQ 0x0800 /* flush queue */
! 128: #define M_MCR_FLQR 0x0004 /* flush queue and report */
! 129: #define M_MCR_SQM 0x0001 /* start queue mode */
! 130:
! 131: /*
! 132: * defines for Interrupt on Queue Available Register
! 133: */
! 134:
! 135: #define M_IQAR_IQEA 0x8000 /* interrupt on queue entry avail */
! 136: #define M_IQAR_IQEH 0x4000 /* interrupt on queue half empty */
! 137: #define M_IQAR_ILVL 0x0700 /* interrupt lvl on queue available */
! 138: #define M_IQAR_IVCT 0x00FF /* interrupt vector on queue avail */
! 139:
! 140: /*
! 141: * defines for Thaw Work Queue Register
! 142: */
! 143:
! 144: #define M_THAW_TWQN 0xff00 /* thaw work queue number */
! 145: #define M_THAW_TWQE 0x0001 /* thaw work queue enable */
! 146:
! 147: typedef struct mcsb
! 148: { /* Master control/Status Block */
! 149: volatile u_short mcsb_MSR; /* Master status register */
! 150: volatile u_short mcsb_MCR; /* Master Control register */
! 151: volatile u_short mcsb_IQAR; /* Interrupt on Queue Available Reg */
! 152: volatile u_short mcsb_QHDP; /* Queue head pointer */
! 153: volatile u_short mcsb_THAW; /* Thaw work Queue */
! 154: volatile u_short mcsb_RES0; /* Reserved word 0 */
! 155: volatile u_short mcsb_RES1; /* Reserved word 1 */
! 156: volatile u_short mcsb_RES2; /* Reserved word 2 */
! 157: } M328_MCSB;
! 158:
! 159: /**************** END Master Control Status Block (MCSB) *******************/
! 160:
! 161: /**************** Scater/Gather Stuff *******************/
! 162:
! 163: typedef struct {
! 164: union {
! 165: unsigned short bytes :16;
! 166: #define MAX_SG_BLOCK_SIZE (1<<16) /* the size *has* to be always *smaller* */
! 167: struct {
! 168: unsigned short :8;
! 169: unsigned short gather :8;
! 170: } scatter;
! 171: } count;
! 172: LONGV address;
! 173: unsigned short link :1;
! 174: unsigned short :3;
! 175: unsigned short transfer_type :2;
! 176: /* 0x0 is reserved */
! 177: #define SHORT_TRANSFER 0x1
! 178: #define LONG_TRANSFER 0x2
! 179: #define SCATTER_GATTER_LIST_IN_SHORT_IO 0x3
! 180: unsigned short memory_type :2;
! 181: #define NORMAL_TYPE 0x0
! 182: #define BLOCK_MODE 0x1
! 183: /* 0x2 is reserved */
! 184: /* 0x3 is reserved */
! 185: unsigned short address_modifier :8;
! 186: }sg_list_element_t;
! 187:
! 188: typedef sg_list_element_t * scatter_gather_list_t;
! 189:
! 190: #define MAX_SG_ELEMENTS 64
! 191:
! 192: struct m328_sg {
! 193: struct m328_sg *up;
! 194: int elements;
! 195: int level;
! 196: struct m328_sg *down[MAX_SG_ELEMENTS];
! 197: sg_list_element_t list[MAX_SG_ELEMENTS];
! 198: };
! 199:
! 200: typedef struct m328_sg *M328_SG;
! 201:
! 202: typedef struct {
! 203: struct scsi_xfer *xs;
! 204: M328_SG top_sg_list;
! 205: } M328_CMD;
! 206: /**************** END Scater/Gather Stuff *******************/
! 207:
! 208: /**************** Host Semaphore Block (HSB) *******************/
! 209:
! 210: typedef struct hsb
! 211: { /* Host Semaphore Block */
! 212: volatile u_short hsb_INITQ; /* Init MCE Flag */
! 213: volatile u_short hsb_WORKQ; /* Work Queue number */
! 214: volatile u_short hsb_MAGIC; /* Magic word */
! 215: volatile u_short hsb_RES0; /* Reserved word */
! 216: } M328_HSB;
! 217:
! 218: /**************** END Host Semaphore Block (HSB) *******************/
! 219:
! 220: /**************** Perform Diagnostics Command Format *******************/
! 221:
! 222: typedef struct pdcf
! 223: { /* Perform Diagnostics Cmd Format */
! 224: volatile u_short pdcf_CMD; /* Command normally 0x40 */
! 225: volatile u_short pdcf_RES0; /* Reserved word */
! 226: volatile u_short pdcf_STATUS; /* Return Status */
! 227: volatile u_short pdcf_RES1; /* Reserved Word */
! 228: volatile u_short pdcf_ROM; /* ROM Test Results */
! 229: volatile u_short pdcf_BUFRAM; /* Buffer RAM results */
! 230: volatile u_short pdcf_EVENT_RAM; /* Event Ram test Results */
! 231: volatile u_short pdcf_SCSI_PRI_PORT; /* SCSI Primary Port Reg test */
! 232: volatile u_short pdcf_SCSI_SEC_PORT; /* SCSI Secondary Port Reg test */
! 233: } M328_PDCF;
! 234:
! 235: #define PDCF_SUCCESS 0xFFFF
! 236:
! 237: /**************** END Perform Diagnostics Command Format *******************/
! 238:
! 239: /*************** Controller Initialization Block (CIB) *****************/
! 240:
! 241: /*
! 242: * defines for Interrupt Vectors
! 243: */
! 244:
! 245: #define M_VECT_ILVL 0x0700 /* Interrupt Level */
! 246: #define M_VECT_IVCT 0x00FF /* Interrupt Vector */
! 247:
! 248: /*
! 249: * defines for SCSI Bus ID Registers
! 250: */
! 251:
! 252: #define M_PSID_DFT 0x0008 /* default ID enable */
! 253: #define M_PSID_ID 0x0007 /* Primary/Secondary SCSI ID */
! 254:
! 255: /*
! 256: * Error recovery flags.
! 257: */
! 258:
! 259: #define M_ERRFLGS_FOSR 0x0001 /* Freeze on SCSI bus reset */
! 260: #define M_ERRFLGS_RIN 0x0002 /* SCSI bus reset interrupt */
! 261: #define M_ERRFLGS_RSE 0x0004 /* Report COUGAR SCSI errors */
! 262:
! 263: /*
! 264: * Controller Initialization Block
! 265: */
! 266:
! 267: typedef struct cib
! 268: {
! 269: volatile u_short cib_NCQE; /* Number of Command Queue Entries */
! 270: volatile u_short cib_BURST; /* DMA Burst count */
! 271: volatile u_short cib_NVECT; /* Normal Completion Vector */
! 272: volatile u_short cib_EVECT; /* Error Completion Vector */
! 273: volatile u_short cib_PID; /* Primary SCSI Bus ID */
! 274: volatile u_short cib_SID; /* Secondary SCSI Bus ID */
! 275: volatile u_short cib_CRBO; /* Command Response Block Offset */
! 276: volatile u_short cib_SELECT_msw;/* Selection timeout in milli_second */
! 277: volatile u_short cib_SELECT_lsw;/* Selection timeout in milli_second */
! 278: volatile u_short cib_WQ0TIMO_msw;/* Work Q - timeout in 256 ms */
! 279: volatile u_short cib_WQ0TIMO_lsw;/* Work Q - timeout in 256 ms */
! 280: volatile u_short cib_VMETIMO_msw;/* VME Time out in 32 ms */
! 281: volatile u_short cib_VMETIMO_lsw;/* VME Time out in 32 ms */
! 282: volatile u_short cib_RES0[2]; /* Reserved words */
! 283: volatile u_short cib_OBMT; /* offbrd CRB mtype/xfer type/ad mod */
! 284: volatile u_short cib_OBADDR_msw;/* host mem address for offboard CRB */
! 285: volatile u_short cib_OBADDR_lsw;/* host mem address for offboard CRB */
! 286: volatile u_short cib_ERR_FLGS; /* error recovery flags */
! 287: volatile u_short cib_RES1; /* reserved word */
! 288: volatile u_short cib_RES2; /* reserved word */
! 289: volatile u_short cib_SBRIV; /* SCSI Bus Reset Interrupt Vector */
! 290: volatile u_char cib_SOF0; /* Synchronous offset (Bus 0) */
! 291: volatile u_char cib_SRATE0; /* Sync negotiation rate (Bus 0) */
! 292: volatile u_char cib_SOF1; /* Synchronous offset (Bus 1) */
! 293: volatile u_char cib_SRATE1; /* Sync negotiation rate (Bus 1) */
! 294: } M328_CIB;
! 295:
! 296: /**************** END Controller Initialization Block (CIB) *****************/
! 297:
! 298: /**************** Command Queue Entry (CQE) *******************/
! 299:
! 300: /*
! 301: * defines for Queue Entry Control Register
! 302: */
! 303:
! 304: #define M_QECR_IOPB 0x0F00 /* IOPB type (must be zero) */
! 305: #define M_QECR_HPC 0x0004 /* High Priority command */
! 306: #define M_QECR_AA 0x0002 /* abort acknowledge */
! 307: #define M_QECR_GO 0x0001 /* Go/Busy */
! 308:
! 309: #define CQE_GO(qecr) ((qecr) |= M_QECR_GO)
! 310: #define CQE_AA_GO(qecr) ((qecr) |= (M_QECR_GO + M_QECR_AA))
! 311:
! 312: typedef struct cqe
! 313: { /* Command Queue Entry */
! 314: volatile u_short cqe_QECR; /* Queue Entry Control Register */
! 315: volatile u_short cqe_IOPB_ADDR; /* IOPB Address */
! 316: volatile LONGV cqe_CTAG; /* Command Tag */
! 317: volatile u_char cqe_IOPB_LENGTH;/* IOPB Length */
! 318: volatile u_char cqe_WORK_QUEUE; /* Work Queue Number */
! 319: volatile u_short cqe_RES0; /* Reserved word */
! 320: } M328_CQE;
! 321:
! 322: /**************** END Command Queue Entry (CQE) *******************/
! 323:
! 324: /**************** Command Response Block (CRB) *******************/
! 325:
! 326: /*
! 327: * defines for Command Response Status Word
! 328: */
! 329:
! 330: #define M_CRSW_SE 0x0800 /* SCSI error (COUGAR) */
! 331: #define M_CRSW_RST 0x0400 /* SCSI Bus reset (COUGAR) */
! 332: #define M_CRSW_SC 0x0080 /* status change */
! 333: #define M_CRSW_CQA 0x0040 /* Command queue entry available */
! 334: #define M_CRSW_QMS 0x0020 /* queue mode started */
! 335: #define M_CRSW_AQ 0x0010 /* abort queue */
! 336: #define M_CRSW_EX 0x0008 /* exception */
! 337: #define M_CRSW_ER 0x0004 /* error */
! 338: #define M_CRSW_CC 0x0002 /* command complete */
! 339: #define M_CRSW_CRBV 0x0001 /* cmd response block valid/clear */
! 340:
! 341: #define CRB_CLR_DONE(crsw) ((crsw) = 0)
! 342: #define CRB_CLR_ER(crsw) ((crsw) &= ~M_CRSW_ER)
! 343:
! 344: typedef struct crb
! 345: { /* Command Response Block */
! 346: volatile u_short crb_CRSW; /* Command Response Status Word */
! 347: volatile u_short crb_RES0; /* Reserved word */
! 348: volatile LONGV crb_CTAG; /* Command Tag */
! 349: volatile u_char crb_IOPB_LENGTH;/* IOPB Length */
! 350: volatile u_char crb_WORK_QUEUE; /* Work Queue Number */
! 351: volatile u_short crb_RES1; /* Reserved word */
! 352: } M328_CRB;
! 353:
! 354: /**************** END Command Response Block (CRB) *******************/
! 355:
! 356: /*********** Controller Error Vector Status Block (CEVSB) **************/
! 357:
! 358: typedef struct cevsb
! 359: { /* Command Response Block */
! 360: volatile u_short cevsb_CRSW; /* Command Response Status Word */
! 361: volatile u_char cevsb_TYPE; /* IOPB type */
! 362: volatile u_char cevsb_RES0; /* Reserved byte */
! 363: volatile LONGV cevsb_CTAG; /* Command Tag */
! 364: volatile u_char cevsb_IOPB_LENGTH;/* IOPB Length */
! 365: volatile u_char cevsb_WORK_QUEUE;/* Work Queue Number */
! 366: volatile u_short cevsb_RES1; /* Reserved word */
! 367: volatile u_char cevsb_RES2; /* Reserved byte */
! 368: volatile u_char cevsb_ERROR; /* error code */
! 369: volatile u_short cevsb_AUXERR; /* COUGAR error code */
! 370: } M328_CEVSB;
! 371:
! 372: /*********** END Controller Error Vector Status Block (CEVSB) **************/
! 373:
! 374: /**************** Configuration Status Block (CSB) *******************/
! 375:
! 376: typedef struct csb
! 377: { /* Configuration Status Blk */
! 378: volatile u_short csb_TYPE; /* 0x0=JAGUAR, 0x4220=COUGAR */
! 379: volatile u_char csb_RES1; /* Reserved byte */
! 380: volatile u_char csb_PCODE[3]; /* Product Code */
! 381: volatile u_short csb_RES2; /* Reserved word */
! 382: volatile u_char csb_RES3; /* Reserved byte */
! 383: volatile u_char csb_PVAR; /* Product Variation */
! 384: volatile u_short csb_RES4; /* Reserved word */
! 385: volatile u_char csb_RES5; /* Reserved byte */
! 386: volatile u_char csb_FREV[3]; /* Firmware Revision level */
! 387: volatile u_short csb_RES6; /* Reserved word */
! 388: volatile u_char csb_FDATE[8]; /* Firmware Release date */
! 389: volatile u_short csb_SSIZE; /* System memory size in Kbytes */
! 390: volatile u_short csb_BSIZE; /* Buffer memory size in Kbytes */
! 391: volatile u_short csb_RES8; /* Reserved word */
! 392: volatile u_char csb_PFECID; /* Primary Bus FEC ID */
! 393: volatile u_char csb_SFECID; /* Secondard Bus FEC ID */
! 394: volatile u_char csb_PID; /* Primary Bus ID */
! 395: volatile u_char csb_SID; /* Secondary Bus ID */
! 396: volatile u_char csb_LPDS; /* Last Primary Device Selected */
! 397: volatile u_char csb_LSDS; /* Last Secondary Device Selected */
! 398: volatile u_char csb_PPS; /* Primary Phase Sense */
! 399: volatile u_char csb_SPS; /* Secondary Phase Sense */
! 400: volatile u_char csb_RES10; /* Reserved byte */
! 401: volatile u_char csb_DBID; /* Daughter Board ID */
! 402: volatile u_char csb_RES11; /* Reserved byte */
! 403: volatile u_char csb_SDS; /* Software DIP Switch */
! 404: volatile u_short csb_RES12; /* Reserved word */
! 405: volatile u_short csb_FWQR; /* Frozen Work Queues Register */
! 406: volatile u_char csb_RES13[72]; /* Reserved bytes */
! 407: } M328_CSB;
! 408:
! 409: /**************** END Configuration Status Block (CSB) *******************/
! 410:
! 411: /**************** IOPB Format (IOPB) *******************/
! 412:
! 413: /*
! 414: * defines for IOPB Option Word
! 415: */
! 416:
! 417: #define M_OPT_HEAD_TAG 0x3000 /* head of queue command queue tag */
! 418: #define M_OPT_ORDERED_TAG 0x2000 /* order command queue tag */
! 419: #define M_OPT_SIMPLE_TAG 0x1000 /* simple command queue tag */
! 420: #define M_OPT_GO_WIDE 0x0800 /* use WIDE transfers */
! 421: #define M_OPT_DIR 0x0100 /* VME direction bit */
! 422: #define M_OPT_SG_BLOCK 0x0008 /* scatter/gather in 512 byte blocks */
! 423: #define M_OPT_SS 0x0004 /* Suppress synchronous transfer */
! 424: #define M_OPT_SG 0x0002 /* scatter/gather bit */
! 425: #define M_OPT_IE 0x0001 /* Interrupt enable */
! 426:
! 427: /*
! 428: * defines for IOPB Address Type and Modifier
! 429: */
! 430:
! 431: #define M_ADR_TRANS 0x0C00 /* transfer type */
! 432: #define M_ADR_MEMT 0x0300 /* memory type */
! 433: #define M_ADR_MOD 0x00FF /* VME address modifier */
! 434: #define M_ADR_SG_LINK 0x8000 /* Scatter/Gather Link bit */
! 435:
! 436: /*
! 437: * defines for IOPB Unit Address on SCSI Bus
! 438: */
! 439:
! 440: #define M_UNIT_EXT_LUN 0xFF00 /* Extended Address */
! 441: #define M_UNIT_EXT 0x0080 /* Extended Address Enable */
! 442: #define M_UNIT_BUS 0x0040 /* SCSI Bus Selection */
! 443: #define M_UNIT_LUN 0x0038 /* Logical Unit Number */
! 444: #define M_UNIT_ID 0x0007 /* SCSI Device ID */
! 445:
! 446: typedef struct short_iopb
! 447: {
! 448: volatile u_short iopb_CMD; /* IOPB Command code */
! 449: volatile u_short iopb_OPTION; /* IOPB Option word */
! 450: volatile u_short iopb_STATUS; /* IOPB Return Status word */
! 451: volatile u_short iopb_RES0; /* IOPB Reserved word */
! 452: volatile u_char iopb_NVCT; /* IOPB Normal completion Vector */
! 453: volatile u_char iopb_EVCT; /* IOPB Error completion Vector */
! 454: volatile u_short iopb_LEVEL; /* IOPB Interrupt Level */
! 455: volatile u_short iopb_RES1; /* IOPB Reserved word */
! 456: volatile u_short iopb_ADDR; /* IOPB Address type and modifer */
! 457: volatile LONGV iopb_BUFF; /* IOPB Buffer Address */
! 458: volatile LONGV iopb_LENGTH; /* IOPB Max-Transfer Length */
! 459: volatile LONGV iopb_SGTTL; /* IOPB Scatter/Gather Total Transfer len */
! 460: volatile u_short iopb_RES4; /* IOPB Reserved word */
! 461: volatile u_short iopb_UNIT; /* IOPB Unit address on SCSI bus */
! 462: } M328_short_IOPB;
! 463:
! 464: typedef struct iopb
! 465: {
! 466: volatile u_short iopb_CMD; /* IOPB Command code */
! 467: volatile u_short iopb_OPTION; /* IOPB Option word */
! 468: volatile u_short iopb_STATUS; /* IOPB Return Status word */
! 469: volatile u_short iopb_RES0; /* IOPB Reserved word */
! 470: volatile u_char iopb_NVCT; /* IOPB Normal completion Vector */
! 471: volatile u_char iopb_EVCT; /* IOPB Error completion Vector */
! 472: volatile u_short iopb_LEVEL; /* IOPB Interrupt Level */
! 473: volatile u_short iopb_RES1; /* IOPB Reserved word */
! 474: volatile u_short iopb_ADDR; /* IOPB Address type and modifer */
! 475: volatile LONGV iopb_BUFF; /* IOPB Buffer Address */
! 476: volatile LONGV iopb_LENGTH; /* IOPB Max-Transfer Length */
! 477: volatile LONGV iopb_SGTTL; /* IOPB Scatter/Gather Total Transfer len */
! 478: volatile u_short iopb_RES4; /* IOPB Reserved word */
! 479: volatile u_short iopb_UNIT; /* IOPB Unit address on SCSI bus */
! 480: u_short iopb_SCSI[S_IOPB_RES/2]; /* IOPB SCSI words for pass thru */
! 481: } M328_IOPB;
! 482:
! 483: /**************** END IOPB Format (IOPB) *******************/
! 484:
! 485: /**************** Initialize Work Queue Command Format (WQCF) ***********/
! 486:
! 487: #define M_WOPT_IWQ 0x8000 /* initialize work queue */
! 488: #define M_WOPT_PE 0x0008 /* parity check enable */
! 489: #define M_WOPT_FE 0x0004 /* freeze on error enable */
! 490: #define M_WOPT_TM 0x0002 /* target mode enable */
! 491: #define M_WOPT_AE 0x0001 /* abort enable */
! 492:
! 493: typedef struct wqcf
! 494: { /* Initialize Work Queue Cmd Format*/
! 495: volatile u_short wqcf_CMD; /* Command Normally (0x42) */
! 496: volatile u_short wqcf_OPTION; /* Command Options */
! 497: volatile u_short wqcf_STATUS; /* Return Status */
! 498: volatile u_short wqcf_RES0; /* Reserved word */
! 499: volatile u_char wqcf_NVCT; /* Normal Completion Vector */
! 500: volatile u_char wqcf_EVCT; /* Error Completion Vector */
! 501: volatile u_short wqcf_ILVL; /* Interrupt Level */
! 502: volatile u_short wqcf_RES1[8]; /* Reserved words */
! 503: volatile u_short wqcf_WORKQ; /* Work Queue Number */
! 504: volatile u_short wqcf_WOPT; /* Work Queue Options */
! 505: volatile u_short wqcf_SLOTS; /* Number of slots in Work Queues */
! 506: volatile u_short wqcf_RES2; /* Reserved word */
! 507: volatile LONGV wqcf_CMDTO; /* Command timeout */
! 508: volatile u_short wqcf_RES3; /* Reserved word */
! 509: } M328_WQCF;
! 510:
! 511: /**************** END Initialize Work Queue Command Format (WQCF) ***********/
! 512:
! 513: /**************** SCSI Reset Command Format (SRCF) ***********/
! 514:
! 515: typedef struct srcf
! 516: { /* SCSI Reset Cmd Format*/
! 517: volatile u_short srcf_CMD; /* Command Normally (0x22) */
! 518: volatile u_short srcf_OPTION; /* Command Options */
! 519: volatile u_short srcf_STATUS; /* Return Status */
! 520: volatile u_short srcf_RES0; /* Reserved word */
! 521: volatile u_char srcf_NVCT; /* Normal Completion Vector */
! 522: volatile u_char srcf_EVCT; /* Error Completion Vector */
! 523: volatile u_short srcf_ILVL; /* Interrupt Level */
! 524: volatile u_short srcf_RES1[8]; /* Reserved words */
! 525: volatile u_short srcf_BUSID; /* SCSI bus ID to reset */
! 526: } M328_SRCF;
! 527:
! 528: /**************** END SCSI Reset Command Format (SRCF) ***********/
! 529:
! 530: /**************** Device Reinitialize Command Format (DRCF) ***********/
! 531:
! 532: typedef struct drcf
! 533: { /* Device Reinitialize Cmd Format*/
! 534: volatile u_short drcf_CMD; /* Command Normally (0x4C) */
! 535: volatile u_short drcf_OPTION; /* Command Options */
! 536: volatile u_short drcf_STATUS; /* Return Status */
! 537: volatile u_short drcf_RES0; /* Reserved word */
! 538: volatile u_char drcf_NVCT; /* Normal Completion Vector */
! 539: volatile u_char drcf_EVCT; /* Error Completion Vector */
! 540: volatile u_short drcf_ILVL; /* Interrupt Level */
! 541: volatile u_short drcf_RES1[9]; /* Reserved words */
! 542: volatile u_short drcf_UNIT; /* Unit Address */
! 543: } M328_DRCF;
! 544:
! 545: /**************** END SCSI Reset Command Format (SRCF) ***********/
! 546:
! 547: /**************** Host Down Loadable Firmware (HDLF) ***********/
! 548:
! 549: typedef struct hdlf
! 550: { /* Host Down Loadable Firmware cmd */
! 551: volatile u_short hdlf_CMD; /* Command Normally (0x4F) */
! 552: volatile u_short hdlf_OPTION; /* Command Options */
! 553: volatile u_short hdlf_STATUS; /* Return Status */
! 554: volatile u_short hdlf_RES0; /* Reserved word */
! 555: volatile u_char hdlf_NVCT; /* Normal Completion Vector */
! 556: volatile u_char hdlf_EVCT; /* Error Completion Vector */
! 557: volatile u_short hdlf_ILVL; /* Interrupt Level */
! 558: volatile u_short hdlf_RES1; /* Reserved word */
! 559: volatile u_short hdlf_ADDR; /* Address type and modifer */
! 560: volatile LONGV hdlf_BUFF; /* Buffer Address */
! 561: volatile LONGV hdlf_LENGTH; /* Max-Transfer Length */
! 562: volatile LONGV hdlf_CSUM; /* Checksum */
! 563: volatile u_short hdlf_RES2; /* Reserved word */
! 564: volatile u_short hdlf_SEQ; /* Sequence number */
! 565: volatile u_short hdlf_RES3[6]; /* Reserved words */
! 566: } M328_HDLF;
! 567:
! 568: #define M328_INITIALIZE_DOWNLOAD 0x0010
! 569: #define M328_TRANSFER_PACKET 0x0020
! 570: #define M328_PROGRAM_FLASH 0x0040
! 571: #define M328_MOTOROLA_S_RECORDS 0x1000
! 572:
! 573: /**************** END SCSI Reset Command Format (SRCF) ***********/
! 574:
! 575: /**************** Short I/O Format *******************/
! 576:
! 577: struct vsreg
! 578: {
! 579: M328_MCSB sh_MCSB; /* Master Control / Status Block */
! 580: M328_CQE sh_MCE; /* Master Command Entry */
! 581: M328_CQE sh_CQE[NUM_CQE]; /* Command Queue Entry */
! 582: M328_IOPB sh_IOPB[NUM_IOPB]; /* Host IOPB Space */
! 583: M328_IOPB sh_MCE_IOPB; /* Host MCE IOPB Space */
! 584: M328_CIB sh_CIB; /* Controller Initialization Block */
! 585: volatile u_char sh_HUS[S_HUS_FREE];/* Host Usable Space */
! 586: M328_HSB sh_HSB; /* Host Semaphore Block */
! 587: M328_CRB sh_CRB; /* Command Response Block */
! 588: M328_IOPB sh_RET_IOPB; /* Returned IOPB */
! 589: M328_CSB sh_CSS; /* Controller Specific Space/Block */
! 590: };
! 591:
! 592: #define CRSW sc->sc_vsreg->sh_CRB.crb_CRSW
! 593: #define THAW_REG sc->sc_vsreg->sh_MCSB.mcsb_THAW
! 594: #define THAW(x) THAW_REG=((u_char)x << 8);THAW_REG |= M_THAW_TWQE
! 595: #define QUEUE_FZN(x) (sc->sc_vsreg->sh_CSS.csb_FWQR & (1 << x))
! 596: #define SELECTION_TIMEOUT 250 /* milliseconds */
! 597: #define VME_BUS_TIMEOUT 0xF /* units of 30ms */
! 598: #define M328_INFINITE_TIMEOUT 0 /* wait forever */
! 599:
! 600: /**************** END Short I/O Format *******************/
! 601:
! 602: /*
! 603: * Scatter gather structure
! 604: */
! 605:
! 606: typedef struct ipsg
! 607: {
! 608: volatile u_short sg_count; /* byte/entry count */
! 609: volatile u_short sg_addrhi; /* datablock/entry address high */
! 610: volatile u_short sg_addrlo; /* datablock/entry address low */
! 611: volatile u_short sg_meminfo; /* memory information */
! 612: }IPSG;
! 613:
! 614: #define MACSI_SG 256 /* number of MACSI scat/gat entries */
! 615: #define S_MACSI_SG (MACSI_SG * sizeof(IPSG))
! 616: #define MACSI_SG_RSIZE 65535 /* max len of each scatter/gather entry */
! 617:
! 618: /*
! 619: * SCSI IOPB definitions
! 620: */
! 621:
! 622: #define IOPB_PASS_THRU 0x20 /* SCSI Pass Through commands */
! 623: #define IOPB_PASS_THRU_EXT 0x21 /* SCSI Pass Through Extended commands */
! 624: #define IOPB_RESET 0x22 /* SCSI Reset bus */
! 625:
! 626: /*
! 627: * SCSI Control IOPB's
! 628: */
! 629:
! 630: #define CNTR_DIAG 0x40 /* Perform Diagnostics */
! 631: #define CNTR_INIT 0x41 /* Initialize Controller */
! 632: #define CNTR_INIT_WORKQ 0x42 /* Initialize Work Queue */
! 633: #define CNTR_DUMP_INIT 0x43 /* Dump Initialization Parameters */
! 634: #define CNTR_DUMP_WORDQ 0x44 /* Dump work Queue Parameters */
! 635: #define CNTR_CANCEL_IOPB 0x48 /* Cancel command tag */
! 636: #define CNTR_FLUSH_WORKQ 0x49 /* Flush Work Queue */
! 637: #define CNTR_DEV_REINIT 0x4C /* Reinitialize Device */
! 638: #define CNTR_ISSUE_ABORT 0x4E /* An abort has been issued */
! 639: #define CNTR_DOWNLOAD_FIRMWARE 0x4F /* Download firmware (COUGAR) */
! 640:
! 641:
! 642: /*
! 643: * Memory types
! 644: */
! 645:
! 646: #define MEMT_16BIT 1 /* 16 Bit Memory type */
! 647: #define MEMT_32BIT 2 /* 32 Bit Memory type */
! 648: #define MEMT_SHIO 3 /* Short I/O Memory type */
! 649: #define MEMTYPE MEMT_32BIT /* do 32-bit transfers */
! 650:
! 651: /*
! 652: * Transfer types
! 653: */
! 654:
! 655: #define TT_NORMAL 0 /* Normal Mode Transfers */
! 656: #define TT_BLOCK 1 /* block Mode Transfers */
! 657: #define TT_DISABLE_INC_ADDR 2 /* Disable Incrementing Addresses */
! 658: #define TT_D64 3 /* D64 Mode Transfers */
! 659:
! 660: /*
! 661: * Error codes.
! 662: */
! 663:
! 664: #define MACSI_GOOD_STATUS 0x00 /* Good status */
! 665: #define MACSI_QUEUE_FULL 0x01 /* The work queue is full */
! 666: #define MACSI_CMD_CODE_ERR 0x04 /* The IOPB command field is invalid */
! 667: #define MACSI_QUEUE_NUMBER_ERR 0x05 /* Invalid queue number */
! 668:
! 669: #define RESET_BUS_STATUS 0x11 /* SCSI bus reset IOPB forced this */
! 670: #define NO_SECONDARY_PORT 0x12 /* second SCSI bus not available */
! 671: #define SCSI_DEVICE_IS_RESET 0x14 /* device has been reset */
! 672: #define CMD_ABORT_BY_RESET 0x15 /* device has been reset */
! 673:
! 674: #define VME_BUS_ERROR 0x20 /* There was a VME BUS error */
! 675: #define VME_BUS_ACC_TIMEOUT 0x21
! 676: #define VME_BUS_BAD_ADDR 0x23
! 677: #define VME_BUS_BAD_MEM_TYPE 0x24
! 678: #define VME_BUS_BAD_COUNT 0x25
! 679: #define VME_BUS_FETCH_ERROR 0x26
! 680: #define VME_BUS_FETCH_TIMEOUT 0x27
! 681: #define VME_BUS_POST_ERROR 0x28
! 682: #define VME_BUS_POST_TIMEOUT 0x29
! 683: #define VME_BUS_BAD_FETCH_ADDR 0x2A
! 684: #define VME_BUS_BAD_POST_ADDR 0x2B
! 685: #define VME_BUS_SG_FETCH 0x2C
! 686: #define VME_BUS_SG_TIMEOUT 0x2D
! 687: #define VME_BUS_SG_COUNT 0x2E
! 688:
! 689: #define SCSI_SELECTION_TO 0x30 /* select time out */
! 690: #define SCSI_DISCONNECT_TIMEOUT 0x31 /* disconnect timeout */
! 691: #define SCSI_ABNORMAL_SEQ 0x32 /* abnormal sequence */
! 692: #define SCSI_DISCONNECT_ERR 0x33 /* disconnect error */
! 693: #define SCSI_XFER_EXCEPTION 0x34 /* transfer cnt exception */
! 694: #define SCSI_PARITY_ERROR 0x35 /* parity error */
! 695:
! 696: #define DEVICE_NO_IOPB 0x82 /* IOPB no available */
! 697: #define IOPB_CTLR_EHX 0x83 /* IOPB counter exhausted */
! 698: #define IOPB_DIR_ERROR 0x84 /* IOPB direction wrong */
! 699: #define COUGAR_ERROR 0x86 /* COUGAR unrecoverable error */
! 700: #define MACSI_INCORRECT_HARDWARE 0x90 /* Insufficient memory */
! 701: #define MACSI_ILGL_IOPB_VAL 0x92 /* Invalid field in the IOPB */
! 702: #define MACSI_ILLEGAL_IMAGE 0x9C /* Submitted fails reuested action */
! 703: #define IOPB_TYPE_ERR 0xC0 /* IOPB type not 0 */
! 704: #define IOPB_TIMEOUT 0xC1 /* IOPB timed out */
! 705:
! 706: #define COUGAR_PANIC 0xFF /* COUGAR paniced */
! 707:
! 708: #define MACSI_INVALID_TIMEOUT 0x843 /* The SCSI byte to byte timer expired */
! 709:
! 710: /*
! 711: * Handy vector macro.
! 712: */
! 713:
! 714: #define VEC(c, vec) (((c) -> mc_ipl << 8) + (vec))
! 715:
! 716: /*
! 717: * VME addressing modes
! 718: */
! 719:
! 720: #define ADRM_STD_S_P 0x3E /* Standard Supervisory Program */
! 721: #define ADRM_STD_S_D 0x3D /* Standard Supervisory Data */
! 722: #define ADRM_STD_N_P 0x3A /* Standard Normal Program */
! 723: #define ADRM_STD_N_D 0x39 /* Standard Normal Data */
! 724: #define ADRM_SHT_S_IO 0x2D /* Short Supervisory IO */
! 725: #define ADRM_SHT_N_IO 0x29 /* Short Normal IO */
! 726: #define ADRM_EXT_S_P 0x0E /* Extended Supervisory Program */
! 727: #define ADRM_EXT_S_D 0x0D /* Extended Supervisory Data */
! 728: #define ADRM_EXT_N_P 0x0A /* Extended Normal Program */
! 729: #define ADRM_EXT_N_D 0x09 /* Extended Normal Data */
! 730: #define ADRM_EXT_S_BM 0x0F /* Extended Supervisory Block Mode */
! 731: #define ADRM_EXT_S_D64 0x0C /* Extended Supervisory D64 Mode */
! 732:
! 733: #define ADDR_MOD ( (TT_NORMAL << 10) | (MEMTYPE << 8) | ADRM_EXT_S_D )
! 734: #define BLOCK_MOD ( (TT_BLOCK << 10) | (MEMTYPE << 8) | ADRM_EXT_S_BM )
! 735: #define D64_MOD ( (TT_D64 << 10) | (MEMTYPE << 8) | ADRM_EXT_S_D64 )
! 736: #define SHIO_MOD ( (TT_NORMAL << 10) | (MEMT_SHIO << 8) | ADRM_SHT_N_IO)
! 737:
! 738: /*
! 739: * Scatter/gather functions
! 740: */
! 741:
! 742: M328_SG vs_alloc_scatter_gather(void);
! 743: void vs_dealloc_scatter_gather(M328_SG sg);
! 744: M328_SG vs_build_memory_structure(struct scsi_xfer *xs, M328_IOPB *iopb);
! 745:
! 746: #endif /* _M328REG_H_ */
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