Annotation of sys/arch/mvme68k/dev/sshreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: sshreg.h,v 1.5 2005/11/21 21:52:45 miod Exp $ */
2:
3: /*
4: * Copyright (c) 1995 Theo de Raadt
5: * Copyright (c) 1990 The Regents of the University of California.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to Berkeley by
9: * Van Jacobson of Lawrence Berkeley Laboratory.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. Neither the name of the University nor the names of its contributors
20: * may be used to endorse or promote products derived from this software
21: * without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33: * SUCH DAMAGE.
34: *
35: * @(#)sshreg.h 7.3 (Berkeley) 2/5/91
36: */
37:
38: /*
39: * NCR 53C710 SCSI interface hardware description.
40: *
41: * From the Mach scsi driver for the 53C700
42: */
43:
44: typedef struct {
45: /*00*/ volatile unsigned char ssh_sien; /* rw: SCSI Interrupt Enable */
46: /*01*/ volatile unsigned char ssh_sdid; /* rw: SCSI Destination ID */
47: /*02*/ volatile unsigned char ssh_scntl1; /* rw: SCSI control reg 1 */
48: /*03*/ volatile unsigned char ssh_scntl0; /* rw: SCSI control reg 0 */
49: /*04*/ volatile unsigned char ssh_socl; /* rw: SCSI Output Control Latch */
50: /*05*/ volatile unsigned char ssh_sodl; /* rw: SCSI Output Data Latch */
51: /*06*/ volatile unsigned char ssh_sxfer; /* rw: SCSI Transfer reg */
52: /*07*/ volatile unsigned char ssh_scid; /* rw: SCSI Chip ID reg */
53: /*08*/ volatile unsigned char ssh_sbcl; /* ro: SCSI Bus Control Lines */
54: /*09*/ volatile unsigned char ssh_sbdl; /* ro: SCSI Bus Data Lines */
55: /*0a*/ volatile unsigned char ssh_sidl; /* ro: SCSI Input Data Latch */
56: /*0b*/ volatile unsigned char ssh_sfbr; /* ro: SCSI First Byte Received */
57: /*0c*/ volatile unsigned char ssh_sstat2; /* ro: SCSI status reg 2 */
58: /*0d*/ volatile unsigned char ssh_sstat1; /* ro: SCSI status reg 1 */
59: /*0e*/ volatile unsigned char ssh_sstat0; /* ro: SCSI status reg 0 */
60: /*0f*/ volatile unsigned char ssh_dstat; /* ro: DMA status */
61: /*10*/ volatile unsigned long ssh_dsa; /* rw: Data Structure Address */
62: /*14*/ volatile unsigned char ssh_ctest3; /* ro: Chip test register 3 */
63: /*15*/ volatile unsigned char ssh_ctest2; /* ro: Chip test register 2 */
64: /*16*/ volatile unsigned char ssh_ctest1; /* ro: Chip test register 1 */
65: /*17*/ volatile unsigned char ssh_ctest0; /* ro: Chip test register 0 */
66: /*18*/ volatile unsigned char ssh_ctest7; /* rw: Chip test register 7 */
67: /*19*/ volatile unsigned char ssh_ctest6; /* rw: Chip test register 6 */
68: /*1a*/ volatile unsigned char ssh_ctest5; /* rw: Chip test register 5 */
69: /*1b*/ volatile unsigned char ssh_ctest4; /* rw: Chip test register 4 */
70: /*1c*/ volatile unsigned long ssh_temp; /* rw: Temporary Stack reg */
71: /*20*/ volatile unsigned char ssh_lcrc; /* rw: LCRC value */
72: /*21*/ volatile unsigned char ssh_ctest8; /* rw: Chip test register 8 */
73: /*22*/ volatile unsigned char ssh_istat; /* rw: Interrupt Status reg */
74: /*23*/ volatile unsigned char ssh_dfifo; /* rw: DMA FIFO */
75: /*24*/ volatile unsigned char ssh_dcmd; /* rw: DMA Command Register */
76: /*25*/ volatile unsigned char ssh_dbc2; /* rw: DMA Byte Counter reg */
77: /*26*/ volatile unsigned char ssh_dbc1;
78: /*27*/ volatile unsigned char ssh_dbc0;
79: /*28*/ volatile unsigned long ssh_dnad; /* rw: DMA Next Address */
80: /*2c*/ volatile unsigned long ssh_dsp; /* rw: DMA SCRIPTS Pointer reg */
81: /*30*/ volatile unsigned long ssh_dsps; /* rw: DMA SCRIPTS Pointer Save reg */
82: /*34*/ volatile unsigned long ssh_scratch; /* rw: Scratch Register */
83: /*38*/ volatile unsigned char ssh_dcntl; /* rw: DMA Control reg */
84: /*39*/ volatile unsigned char ssh_dwt; /* rw: DMA Watchdog Timer */
85: /*3a*/ volatile unsigned char ssh_dien; /* rw: DMA Interrupt Enable */
86: /*3b*/ volatile unsigned char ssh_dmode; /* rw: DMA Mode reg */
87: /*3c*/ volatile unsigned long ssh_adder;
88:
89: } ssh_regmap_t;
90: typedef volatile ssh_regmap_t *ssh_regmap_p;
91:
92: /*
93: * Register defines
94: */
95:
96: /* Scsi control register 0 (scntl0) */
97:
98: #define SSH_SCNTL0_ARB 0xc0 /* Arbitration mode */
99: # define SSH_ARB_SIMPLE 0x00
100: # define SSH_ARB_FULL 0xc0
101: #define SSH_SCNTL0_START 0x20 /* Start Sequence */
102: #define SSH_SCNTL0_WATN 0x10 /* (Select) With ATN */
103: #define SSH_SCNTL0_EPC 0x08 /* Enable Parity Checking */
104: #define SSH_SCNTL0_EPG 0x04 /* Enable Parity Generation */
105: #define SSH_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */
106: #define SSH_SCNTL0_TRG 0x01 /* Target Mode */
107:
108: /* Scsi control register 1 (scntl1) */
109:
110: #define SSH_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */
111: #define SSH_SCNTL1_ADB 0x40 /* Assert Data Bus */
112: #define SSH_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */
113: #define SSH_SCNTL1_CON 0x10 /* Connected */
114: #define SSH_SCNTL1_RST 0x08 /* Assert RST */
115: #define SSH_SCNTL1_AESP 0x04 /* Assert even SCSI parity */
116: #define SSH_SCNTL1_RES0 0x02 /* Reserved */
117: #define SSH_SCNTL1_RES1 0x01 /* Reserved */
118:
119: /* Scsi interrupt enable register (sien) */
120:
121: #define SSH_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */
122: #define SSH_SIEN_FCMP 0x40 /* Function Complete */
123: #define SSH_SIEN_STO 0x20 /* (Re)Selection timeout */
124: #define SSH_SIEN_SEL 0x10 /* (Re)Selected */
125: #define SSH_SIEN_SGE 0x08 /* SCSI Gross Error */
126: #define SSH_SIEN_UDC 0x04 /* Unexpected Disconnect */
127: #define SSH_SIEN_RST 0x02 /* RST asserted */
128: #define SSH_SIEN_PAR 0x01 /* Parity Error */
129:
130: /* Scsi chip ID (scid) */
131:
132: #define SSH_SCID_VALUE(i) (1<<i)
133:
134: /* Scsi transfer register (sxfer) */
135:
136: #define SSH_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */
137: #define SSH_SXFER_TP 0x70 /* Synch Transfer Period */
138: /* see specs for formulas:
139: Period = TCP * (4 + XFERP )
140: TCP = 1 + CLK + 1..2;
141: */
142: #define SSH_SXFER_MO 0x0f /* Synch Max Offset */
143: # define SSH_MAX_OFFSET 8
144:
145: /* Scsi output data latch register (sodl) */
146:
147: /* Scsi output control latch register (socl) */
148:
149: #define SSH_REQ 0x80 /* SCSI signal <x> asserted */
150: #define SSH_ACK 0x40
151: #define SSH_BSY 0x20
152: #define SSH_SEL 0x10
153: #define SSH_ATN 0x08
154: #define SSH_MSG 0x04
155: #define SSH_CD 0x02
156: #define SSH_IO 0x01
157:
158: #define SSH_PHASE(socl) SCSI_PHASE(socl)
159:
160: /* Scsi first byte received register (sfbr) */
161:
162: /* Scsi input data latch register (sidl) */
163:
164: /* Scsi bus data lines register (sbdl) */
165:
166: /* Scsi bus control lines register (sbcl). Same as socl */
167:
168: /* DMA status register (dstat) */
169:
170: #define SSH_DSTAT_DFE 0x80 /* DMA FIFO empty */
171: #define SSH_DSTAT_RES 0x40
172: #define SSH_DSTAT_BF 0x20 /* Bus fault */
173: #define SSH_DSTAT_ABRT 0x10 /* Aborted */
174: #define SSH_DSTAT_SSI 0x08 /* SCRIPT Single Step */
175: #define SSH_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */
176: #define SSH_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */
177: #define SSH_DSTAT_IID 0x01 /* Invalid Instruction Detected */
178:
179: /* Scsi status register 0 (sstat0) */
180:
181: #define SSH_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */
182: #define SSH_SSTAT0_FCMP 0x40 /* Function Complete */
183: #define SSH_SSTAT0_STO 0x20 /* (Re)Selection timeout */
184: #define SSH_SSTAT0_SEL 0x10 /* (Re)Selected */
185: #define SSH_SSTAT0_SGE 0x08 /* SCSI Gross Error */
186: #define SSH_SSTAT0_UDC 0x04 /* Unexpected Disconnect */
187: #define SSH_SSTAT0_RST 0x02 /* RST asserted */
188: #define SSH_SSTAT0_PAR 0x01 /* Parity Error */
189:
190: /* Scsi status register 1 (sstat1) */
191:
192: #define SSH_SSTAT1_ILF 0x80 /* Input latch (sidl) full */
193: #define SSH_SSTAT1_ORF 0x40 /* output reg (sodr) full */
194: #define SSH_SSTAT1_OLF 0x20 /* output latch (sodl) full */
195: #define SSH_SSTAT1_AIP 0x10 /* Arbitration in progress */
196: #define SSH_SSTAT1_LOA 0x08 /* Lost arbitration */
197: #define SSH_SSTAT1_WOA 0x04 /* Won arbitration */
198: #define SSH_SSTAT1_RST 0x02 /* SCSI RST current value */
199: #define SSH_SSTAT1_SDP 0x01 /* SCSI SDP current value */
200:
201: /* Scsi status register 2 (sstat2) */
202:
203: #define SSH_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */
204: # define SSH_SCSI_FIFO_DEEP 8
205: #define SSH_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */
206: #define SSH_SSTAT2_MSG 0x04 /* Latched SCSI phase */
207: #define SSH_SSTAT2_CD 0x02
208: #define SSH_SSTAT2_IO 0x01
209:
210: /* Chip test register 0 (ctest0) */
211:
212: #define SSH_CTEST0_RES0 0x80
213: #define SSH_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */
214: #define SSH_CTEST0_GRP 0x20 /* Generate Receive Parity for Passthrough */
215: #define SSH_CTEST0_EAN 0x10 /* Enable Active Negation */
216: #define SSH_CTEST0_HSC 0x08 /* Halt SCSI clock */
217: #define SSH_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */
218: #define SSH_CTEST0_RES1 0x02
219: #define SSH_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */
220:
221: /* Chip test register 1 (ctest1) */
222:
223: #define SSH_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */
224: #define SSH_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */
225:
226: /* Chip test register 2 (ctest2) */
227:
228: #define SSH_CTEST2_RES 0x80
229: #define SSH_CTEST2_SIGP 0x40 /* Signal process */
230: #define SSH_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */
231: #define SSH_CTEST2_SFP 0x10 /* SCSI FIFO Parity */
232: #define SSH_CTEST2_DFP 0x08 /* DMA FIFO Parity */
233: #define SSH_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */
234: #define SSH_CTEST2_DREQ 0x02 /* DREQ status */
235: #define SSH_CTEST2_DACK 0x01 /* DACK status */
236:
237: /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */
238:
239: /* Chip test register 4 (ctest4) */
240:
241: #define SSH_CTEST4_MUX 0x80 /* Host bus multiplex mode */
242: #define SSH_CTEST4_ZMOD 0x40 /* High-impedance outputs */
243: #define SSH_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */
244: #define SSH_CTEST4_SLBE 0x10 /* SCSI loobpack enable */
245: #define SSH_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */
246: #define SSH_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6)
247: 4->0, .. 7->3 */
248:
249: /* Chip test register 5 (ctest5) */
250:
251: #define SSH_CTEST5_ADCK 0x80 /* Clock Address Incrementor */
252: #define SSH_CTEST5_BBCK 0x40 /* Clock Byte counter */
253: #define SSH_CTEST5_ROFF 0x20 /* Reset SCSI offset */
254: #define SSH_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */
255: #define SSH_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */
256: #define SSH_CTEST5_EOP 0x04 /* (re)set internal EOP */
257: #define SSH_CTEST5_DREQ 0x02 /* (re)set internal REQ */
258: #define SSH_CTEST5_DACK 0x01 /* (re)set internal ACK */
259:
260: /* Chip test register 6 (ctest6) DMA FIFO access */
261:
262: /* Chip test register 7 (ctest7) */
263:
264: #define SSH_CTEST7_CDIS 0x80 /* Cache burst disable */
265: #define SSH_CTEST7_SC1 0x40 /* Snoop control 1 */
266: #define SSH_CTEST7_SC0 0x20 /* Snoop control 0 */
267: #define SSH_CTEST7_INHIBIT (0 << 5)
268: #define SSH_CTEST7_SNOOP (1 << 5)
269: #define SSH_CTEST7_INVAL (2 << 5)
270: #define SSH_CTEST7_RESV (3 << 5)
271: #define SSH_CTEST7_STD 0x10 /* Selection timeout disable */
272: #define SSH_CTEST7_DFP 0x08 /* DMA FIFO parity bit */
273: #define SSH_CTEST7_EVP 0x04 /* Even parity (to host bus) */
274: #define SSH_CTEST7_TT1 0x02 /* Transfer type bit */
275: #define SSH_CTEST7_DIFF 0x01 /* Differential mode */
276:
277: /* DMA FIFO register (dfifo) */
278:
279: #define SSH_DFIFO_RES 0x80
280: #define SSH_DFIFO_BO 0x7f /* FIFO byte offset counter */
281:
282: /* Interrupt status register (istat) */
283:
284: #define SSH_ISTAT_ABRT 0x80 /* Abort operation */
285: #define SSH_ISTAT_RST 0x40 /* Software reset */
286: #define SSH_ISTAT_SIGP 0x20 /* Signal process */
287: #define SSH_ISTAT_RES 0x10
288: #define SSH_ISTAT_CON 0x08 /* Connected */
289: #define SSH_ISTAT_RES1 0x04
290: #define SSH_ISTAT_SIP 0x02 /* SCSI Interrupt pending */
291: #define SSH_ISTAT_DIP 0x01 /* DMA Interrupt pending */
292:
293: /* Chip test register 8 (ctest8) */
294:
295: #define SSH_CTEST8_V 0xf0 /* Chip revision level */
296: #define SSH_CTEST8_FLF 0x08 /* Flush DMA FIFO */
297: #define SSH_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */
298: #define SSH_CTEST8_FM 0x02 /* Fetch pin mode */
299: #define SSH_CTEST8_SM 0x01 /* Snoop pins mode */
300:
301: /* DMA Mode register (dmode) */
302:
303: #define SSH_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */
304: #define SSH_DMODE_FC 0x30 /* Function code */
305: #define SSH_DMODE_PD 0x08 /* Program/data */
306: #define SSH_DMODE_FAM 0x04 /* Fixed address mode */
307: #define SSH_DMODE_U0 0x02 /* User programmable transfer type */
308: #define SSH_DMODE_MAN 0x01 /* Manual start mode */
309:
310: /* DMA interrupt enable register (dien) */
311:
312: #define SSH_DIEN_RES 0xc0
313: #define SSH_DIEN_BF 0x20 /* On Bus Fault */
314: #define SSH_DIEN_ABRT 0x10 /* On Abort */
315: #define SSH_DIEN_SSI 0x08 /* On SCRIPTS sstep */
316: #define SSH_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */
317: #define SSH_DIEN_WTD 0x02 /* On watchdog timeout */
318: #define SSH_DIEN_IID 0x01 /* On illegal instruction detected */
319:
320: /* DMA control register (dcntl) */
321:
322: #define SSH_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers:
323: 0 --> 37.51..50.00 MHz, div=2
324: 1 --> 25.01..37.50 MHz, div=1.5
325: 2 --> 16.67..25.00 MHz, div=1
326: 3 --> 50.01..66.67 MHz, div=3
327: */
328: #define SSH_DCNTL_EA 0x20 /* Enable ack */
329: #define SSH_DCNTL_SSM 0x10 /* Single step mode */
330: #define SSH_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */
331: #define SSH_DCNTL_STD 0x04 /* Start DMA operation */
332: #define SSH_DCNTL_FA 0x02 /* Fast arbitration */
333: #define SSH_DCNTL_COM 0x01 /* 53C700 compatibility */
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