Annotation of sys/arch/mvme68k/dev/pccreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pccreg.h,v 1.7 2004/07/30 22:29:45 miod Exp $ */
2:
3: /*
4: * Copyright (c) 1995 Theo de Raadt
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26: */
27:
28: /*
29: * MVME147 PCC chip
30: */
31: struct pccreg {
32: volatile u_long pcc_dmataddr; /* dma table address */
33: volatile u_long pcc_dmadaddr; /* dma data address */
34: volatile u_long pcc_dmabcnt; /* dma byte count */
35: volatile u_long pcc_dmahold; /* dma data hold register */
36: volatile u_short pcc_t1pload; /* timer1 preload */
37: volatile u_short pcc_t1count; /* timer1 count */
38: volatile u_short pcc_t2pload; /* timer2 preload */
39: volatile u_short pcc_t2count; /* timer2 count */
40: volatile u_char pcc_t1irq; /* timer1 interrupt ctrl */
41: volatile u_char pcc_t1ctl; /* timer1 ctrl reg */
42: volatile u_char pcc_t2irq; /* timer2 interrupt ctrl */
43: volatile u_char pcc_t2ctl; /* timer2 ctrl reg */
44: volatile u_char pcc_acfirq; /* acfail intr reg */
45: volatile u_char pcc_dogirq; /* watchdog intr reg */
46: volatile u_char pcc_lpirq; /* printer intr reg */
47: volatile u_char pcc_lpctl; /* printer ctrl */
48: volatile u_char pcc_dmairq; /* dma interrupt control */
49: volatile u_char pcc_dmacsr; /* dma csr */
50: volatile u_char pcc_busirq; /* bus error interrupt */
51: volatile u_char pcc_dmasr; /* dma status register */
52: volatile u_char pcc_abortirq; /* abort interrupt control reg */
53: volatile u_char pcc_tafcr; /* table address function code reg */
54: volatile u_char pcc_zsirq; /* serial interrupt reg */
55: volatile u_char pcc_genctl; /* general control register */
56: volatile u_char pcc_leirq; /* ethernet interrupt */
57: volatile u_char pcc_gensr; /* general status */
58: volatile u_char pcc_sbicirq; /* sbic interrupt reg */
59: volatile u_char pcc_slavebase; /* slave base addr reg */
60: volatile u_char pcc_sw1inq; /* software interrupt #1 cr */
61: volatile u_char pcc_vecbase; /* interrupt base vector register */
62: volatile u_char pcc_sw2irq; /* software interrupt #2 cr */
63: volatile u_char pcc_chiprev; /* revision level */
64: };
65: #define PCCSPACE_PCCCHIP_OFF 0x1000
66:
67: /*
68: * points to system's PCC. This is not active until the pcc0 device
69: * has been attached.
70: */
71: extern struct pccreg *sys_pcc;
72:
73: /*
74: * We lock off our interrupt vector at 0x40.
75: */
76: #define PCC_VECBASE 0x40
77: #define PCC_NVEC 12
78:
79: /*
80: * Vectors we use
81: */
82: #define PCCV_ACFAIL 0
83: #define PCCV_BERR 1
84: #define PCCV_ABORT 2
85: #define PCCV_ZS 3
86: #define PCCV_LE 4
87: #define PCCV_SBIC 5
88: #define PCCV_DMA 6
89: #define PCCV_PRINTER 7
90: #define PCCV_TIMER1 8
91: #define PCCV_TIMER2 9
92: #define PCCV_SOFT1 10
93: #define PCCV_SOFT2 11
94:
95: #define PCC_DMABCNT_MAKEFC(fcn) ((fcn) << 24)
96: #define PCC_DMABCNT_FCMASK 0x07000000
97: #define PCC_DMABCNT_L 0x80000000
98: #define PCC_DMABCNT_CNTMASK 0x00ffffff
99:
100: #define PCC_DMACSR_DONE 0x80
101: #define PCC_DMACSR_ERR8BIT 0x40
102: #define PCC_DMACSR_TNOT32 0x20
103: #define PCC_DMACSR_DMAERRDATA 0x10
104: #define PCC_DMACSR_DMAERRTABLE 0x08
105: #define PCC_DMACSR_TOSCSI 0x04
106: #define PCC_DMACSR_USETABLE 0x02
107: #define PCC_DMACSR_DEN 0x01
108:
109: #define PCC_SBIC_RESETIRQ 0x40
110: #define PCC_SBIC_RESETABS 0x20
111:
112: /*
113: * Fairly standard irq register bits.
114: */
115: #define PCC_IRQ_IPL 0x07
116: #define PCC_IRQ_IEN 0x08
117: #define PCC_IRQ_INT 0x80
118:
119: #define PCC_LPIRQ_ACK 0x20
120:
121: /*
122: * clock/timer
123: */
124: #define PCC_TIMERACK 0x80 /* ack intr */
125: #define PCC_TIMERCLEAR 0x00 /* reset and clear timer */
126: #define PCC_TIMERSTART 0x03 /* start timer */
127:
128: #define pcc_timer_hz2lim(hz) (65536 - (160000/(hz)))
129: #define pcc_timer_us2lim(us) (65536 - (160000/(1000000/(us))))
130:
131: /*
132: * serial control
133: */
134: #define PCC_ZS_PCCVEC 0x10 /* let PCC supply vector */
135:
136: /*
137: * abort switch
138: */
139: #define PCC_ABORT_IEN 0x08 /* enable interrupt */
140: #define PCC_ABORT_ABS 0x40 /* current state of switch */
141: #define PCC_ABORT_ACK 0x80 /* intr active; or write to ack */
142:
143: /*
144: * for the console we need zs phys addr
145: */
146: #define ZS0_PHYS_147 (INTIOBASE_147 + 0x3000)
147: #define ZS1_PHYS_147 (INTIOBASE_147 + 0x3800)
148:
149: /* XXX */
150: int pccintr_establish(int, struct intrhand *, const char *);
151: int pccspeed(struct pccreg *);
152:
153: #define PCC_GENCTL_IEN 0x10
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