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Annotation of sys/arch/mvme68k/dev/mcreg.h, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: mcreg.h,v 1.9 2004/07/30 22:29:45 miod Exp $ */
                      2:
                      3: /*
                      4:  * Copyright (c) 1995 Theo de Raadt
                      5:  * All rights reserved.
                      6:  *
                      7:  * Redistribution and use in source and binary forms, with or without
                      8:  * modification, are permitted provided that the following conditions
                      9:  * are met:
                     10:  * 1. Redistributions of source code must retain the above copyright
                     11:  *    notice, this list of conditions and the following disclaimer.
                     12:  * 2. Redistributions in binary form must reproduce the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer in the
                     14:  *    documentation and/or other materials provided with the distribution.
                     15:  *
                     16:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
                     17:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
                     18:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
                     19:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
                     20:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
                     21:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
                     22:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
                     23:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
                     24:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
                     25:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                     26:  */
                     27:
                     28: /*
                     29:  * VME162 MCchip
                     30:  */
                     31: struct mcreg {
                     32: /*0x00*/       volatile u_char         mc_chipid;
                     33: /*0x01*/       volatile u_char         mc_chiprev;
                     34: /*0x02*/       volatile u_char         mc_genctl;
                     35: /*0x03*/       volatile u_char         mc_vecbase;
                     36: /*0x04*/       volatile u_long         mc_t1cmp;
                     37: /*0x08*/       volatile u_long         mc_t1count;
                     38: /*0x0C*/       volatile u_long         mc_t2cmp;
                     39: /*0x10*/       volatile u_long         mc_t2count;
                     40: /*0x14*/       volatile u_char         mc_lsbprescale;
                     41: /*0x15*/       volatile u_char         mc_adjprescale;
                     42: /*0x16*/       volatile u_char         mc_t2ctl;
                     43: /*0x17*/       volatile u_char         mc_t1ctl;
                     44: /*0x18*/       volatile u_char         mc_t4irq;
                     45: /*0x19*/       volatile u_char         mc_t3irq;
                     46: /*0x1A*/       volatile u_char         mc_t2irq;
                     47: /*0x1B*/       volatile u_char         mc_t1irq;
                     48: /*0x1C*/       volatile u_char         mc_parity;
                     49: /*0x1D*/       volatile u_char         mc_zsirq;
                     50: /*0x1E*/       volatile u_char         mc_t4ctl;
                     51: /*0x1F*/       volatile u_char         mc_t3ctl;
                     52: /*0x20*/       volatile u_short        mc_drambase;
                     53: /*0x22*/       volatile u_short        mc_srambase;
                     54: /*0x24*/       volatile u_char         mc_dramsize;
                     55: /*0x25*/       volatile u_char         mc_memoptions;
                     56:    #define MC_MEMOPTIONS_SRAMMASK      0x18
                     57:    #define MC_MEMOPTIONS_SRAM128K      0x00
                     58:    #define MC_MEMOPTIONS_SRAM512K      0x08
                     59:    #define MC_MEMOPTIONS_SRAM1M        0x10
                     60:    #define MC_MEMOPTIONS_SRAM2M        0x18
                     61:    #define MC_MEMOPTIONS_DRAMMASK      0x07
                     62:    #define MC_MEMOPTIONS_DRAM1M        0x00
                     63:    #define MC_MEMOPTIONS_DRAM2M        0x01
                     64:    #define MC_MEMOPTIONS_DRAM4M        0x03
                     65:    #define MC_MEMOPTIONS_DRAM4M2       0x04
                     66:    #define MC_MEMOPTIONS_DRAM8M        0x05
                     67:    #define MC_MEMOPTIONS_DRAM16M       0x07
                     68: /*0x26*/       volatile u_char         mc_sramsize;
                     69: /*0x27*/       volatile u_char         mc_resv1;
                     70: /*0x28*/       volatile u_char         mc_ieerr;
                     71: /*0x29*/       volatile u_char         mc_resv2;
                     72: /*0x2A*/       volatile u_char         mc_ieirq;
                     73: /*0x2B*/       volatile u_char         mc_iefailirq;
                     74: /*0x2C*/       volatile u_char         mc_ncrerr;
                     75: /*0x2D*/       volatile u_char         mc_input;
                     76:        #define MC_INPUT_USR1   0x80
                     77:        #define MC_INPUT_USR2   0x40
                     78:        #define MC_INPUT_USR3   0x20
                     79:        #define MC_INPUT_USR4   0x10
                     80:        #define MC_INPUT_PROM   0x08
                     81:        #define MC_INPUT_BUG3   0x04
                     82:        #define MC_INPUT_BUG2   0x02
                     83:        #define MC_INPUT_BUG1   0x01
                     84: /*0x2E*/       volatile u_char         mc_ver;
                     85: /*0x01*/       volatile u_char         mc_ncrirq;
                     86: /*0x01*/       volatile u_long         mc_t3cmp;
                     87: /*0x01*/       volatile u_long         mc_t3count;
                     88: /*0x01*/       volatile u_long         mc_t4cmp;
                     89: /*0x01*/       volatile u_long         mc_t4count;
                     90: /*0x01*/       volatile u_char         mc_busclock;
                     91: /*0x01*/       volatile u_char         mc_promtime;
                     92: /*0x01*/       volatile u_char         mc_flashctl;
                     93:        #define MC_FLASHCTL_WRITE       0x08
                     94: /*0x01*/       volatile u_char         mc_abortirq;
                     95: /*0x01*/       volatile u_char         mc_resetctl;
                     96: /*0x01*/       volatile u_char         mc_watchdogctl;
                     97: /*0x01*/       volatile u_char         mc_watchdogtime;
                     98: /*0x01*/       volatile u_char         mc_resv3;
                     99: /*0x01*/       volatile u_char         mc_dramctl;
                    100: /*0x01*/       volatile u_char         mc_resv4;
                    101: /*0x01*/       volatile u_char         mc_mpustat;
                    102: /*0x01*/       volatile u_char         mc_resv5;
                    103: /*0x01*/       volatile u_long         mc_prescale;
                    104: };
                    105: #define MC_MCCHIP_OFF          0x42000
                    106: #define MC_CHIPID              0x84
                    107:
                    108: /*
                    109:  * points to system's MCchip registers
                    110:  */
                    111: extern struct mcreg *sys_mc;
                    112:
                    113: /*
                    114:  * for the console we need zs phys addr
                    115:  */
                    116: #define ZS0_PHYS_162   (0xfff45000)
                    117: #define ZS1_PHYS_162   (0xfff45801)
                    118:
                    119: /*
                    120:  * We lock off our interrupt vector at 0x50.
                    121:  */
                    122: #define MC_VECBASE     0x50
                    123: #define MC_NVEC                16
                    124:
                    125: #define MCV_ZS         0x00
                    126: #define MCV_TIMER4     0x03
                    127: #define MCV_TIMER3     0x04
                    128: #define MCV_NCR                0x05
                    129: #define MCV_IEFAIL     0x06
                    130: #define MCV_IE         0x07
                    131: #define MCV_TIMER2     0x08
                    132: #define MCV_TIMER1     0x09
                    133: #define MCV_PARITY     0x0b
                    134: #define MCV_ABORT      0x0e
                    135:
                    136: #define MC_TCTL_CEN    0x01
                    137: #define MC_TCTL_COC    0x02
                    138: #define MC_TCTL_COVF   0x04
                    139: #define MC_TCTL_OVF    0xf0
                    140:
                    141: #define        MC_ABORT_ABS    0x40
                    142:
                    143: #define mc_timer_us2lim(us)    (us)            /* timer increments in "us" */
                    144:
                    145: #define MC_IRQ_IPL     0x07
                    146: #define MC_IRQ_ICLR    0x08
                    147: #define MC_IRQ_IEN     0x10
                    148: #define MC_IRQ_INT     0x20
                    149:
                    150: #define MC_GENCTL_IEN  0x02
                    151:
                    152: #define MC_IEERR_SCLR  0x01
                    153:
                    154: #define MC_SC_INHIBIT  (0 << 6)
                    155: #define MC_SC_SNOOP    (1 << 6)
                    156: #define MC_SC_INVAL    (2 << 6)
                    157: #define MC_SC_RESV     (3 << 6)
                    158:
                    159: #define MC_VER_ISLX    0x40
                    160: #define MC_VER_REAL040 0x10
                    161: #define MC_VER_NOIE    0x08
                    162: #define MC_VER_NONCR   0x04
                    163: #define MC_VER_NOVME   0x02
                    164: #define MC_VER_33MHZ   0x01
                    165:
                    166: void mc_enableflashwrite(int on);
                    167: #define MC_ENAFLASHWRITE_OFFSET        0xcc000
                    168: #define MC_DISFLASHWRITE_OFFSET        0xc8000
                    169: int mc_hasflash(void);
                    170:
                    171: int  mcintr_establish(int, struct intrhand *, const char *);

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