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Annotation of sys/arch/mvme68k/dev/if_lereg.h, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: if_lereg.h,v 1.9 2007/05/25 21:27:15 krw Exp $ */
                      2:
                      3: /*-
                      4:  * Copyright (c) 1982, 1992, 1993
                      5:  *     The Regents of the University of California.  All rights reserved.
                      6:  *
                      7:  * Redistribution and use in source and binary forms, with or without
                      8:  * modification, are permitted provided that the following conditions
                      9:  * are met:
                     10:  * 1. Redistributions of source code must retain the above copyright
                     11:  *    notice, this list of conditions and the following disclaimer.
                     12:  * 2. Redistributions in binary form must reproduce the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer in the
                     14:  *    documentation and/or other materials provided with the distribution.
                     15:  * 3. Neither the name of the University nor the names of its contributors
                     16:  *    may be used to endorse or promote products derived from this software
                     17:  *    without specific prior written permission.
                     18:  *
                     19:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
                     20:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
                     21:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
                     22:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
                     23:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
                     24:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
                     25:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
                     26:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
                     27:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
                     28:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
                     29:  * SUCH DAMAGE.
                     30:  *
                     31:  * @(#)if_lereg.h      8.2 (Berkeley) 10/30/93
                     32:  */
                     33:
                     34: #define LEMEMSIZE 0x4000
                     35:
                     36: /*
                     37:  * LANCE registers.
                     38:  */
                     39: struct lereg1 {
                     40:         volatile u_int16_t      ler1_rdp;       /* data port */
                     41:         volatile u_int16_t      ler1_rap;       /* register select port */
                     42: };
                     43:
                     44: #define        VLEMEMSIZE      0x00040000
                     45: #define        VLEMEMBASE      0xfd6c0000
                     46:
                     47: /*
                     48:  * LANCE registers for MVME376
                     49:  */
                     50: struct vlereg1 {
                     51:    volatile u_int16_t      ler1_csr;       /* board control/status register */
                     52:    volatile u_int16_t      ler1_vec;       /* interrupt vector register */
                     53:    volatile u_int16_t      ler1_rdp;       /* data port */
                     54:    volatile u_int16_t      ler1_rap;       /* register select port */
                     55:    volatile u_int16_t      ler1_ear;       /* ethernet address register */
                     56: };
                     57:
                     58: #define NVRAM_EN    0x0008 /* NVRAM enable bit              */
                     59: #define INTR_EN     0x0010 /* Interrupt enable bit          */
                     60: #define PARITYB     0x0020 /* Parity clear bit              */
                     61: #define HW_RS       0x0040 /* Hardware reset bit            */
                     62: #define SYSFAILB    0x0080 /* SYSFAIL bit                   */
                     63: #define NVRAM_RWEL   0xE0  /* Reset write enable latch      */
                     64: #define NVRAM_STO    0x60  /* Store ram to eeprom           */
                     65: #define NVRAM_SLP    0xA0  /* Novram into low power mode    */
                     66: #define NVRAM_WRITE  0x20  /* Writes word from location x   */
                     67: #define NVRAM_SWEL   0xC0  /* Set write enable latch        */
                     68: #define NVRAM_RCL    0x40  /* Recall eeprom data into ram   */
                     69: #define NVRAM_READ   0x00  /* Reads word from location x    */
                     70:
                     71: #define CDELAY  delay(10000)
                     72: #define WRITE_CSR_OR(x)    reg1->ler1_csr=((struct le_softc *)sc)->csr|=x
                     73: #define WRITE_CSR_AND(x)   reg1->ler1_csr=((struct le_softc *)sc)->csr&=x
                     74: #define ENABLE_NVRAM       WRITE_CSR_AND(~NVRAM_EN)
                     75: #define DISABLE_NVRAM      WRITE_CSR_OR(NVRAM_EN)
                     76: #define ENABLE_INTR        WRITE_CSR_AND(~INTR_EN)
                     77: #define DISABLE_INTR       WRITE_CSR_OR(INTR_EN)
                     78: #define RESET_HW           WRITE_CSR_AND(~0xFF00);WRITE_CSR_AND(~HW_RS);CDELAY
                     79: #define SET_IPL(x)         WRITE_CSR_AND(~x)
                     80: #define SET_VEC(x)         reg1->ler1_vec=0;reg1->ler1_vec |=x;
                     81: #define PARITY_CL          WRITE_CSR_AND(~PARITYB)
                     82: #define SYSFAIL_CL         WRITE_CSR_AND(~SYSFAILB)
                     83: #define NVRAM_CMD(c,a)     for(i=0;i<8;i++){ \
                     84:                               reg1->ler1_ear=((c|(a<<1))>>i); \
                     85:                               CDELAY; \
                     86:                            } \
                     87:                            CDELAY;
                     88:
                     89: