Annotation of sys/arch/mips64/mips64/cpu.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cpu.c,v 1.10 2007/05/07 18:42:13 kettenis Exp $ */
2:
3: /*
4: * Copyright (c) 1997-2004 Opsycon AB (www.opsycon.se)
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: *
15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25: * SUCH DAMAGE.
26: *
27: */
28:
29: #include <sys/param.h>
30: #include <sys/systm.h>
31: #include <sys/proc.h>
32: #include <sys/user.h>
33: #include <sys/device.h>
34:
35: #include <machine/pte.h>
36: #include <machine/cpu.h>
37: #include <machine/autoconf.h>
38:
39: int cpumatch(struct device *, void *, void *);
40: void cpuattach(struct device *, struct device *, void *);
41:
42: struct cpu_info cpu_info_primary;
43:
44: u_int CpuPrimaryInstCacheSize;
45: u_int CpuPrimaryInstCacheLSize;
46: u_int CpuPrimaryInstSetSize;
47: u_int CpuPrimaryDataCacheSize;
48: u_int CpuPrimaryDataCacheLSize;
49: u_int CpuPrimaryDataSetSize;
50: u_int CpuCacheAliasMask;
51: u_int CpuSecondaryCacheSize;
52: u_int CpuTertiaryCacheSize;
53: u_int CpuNWayCache;
54: u_int CpuCacheType; /* R4K, R5K, RM7K */
55: u_int CpuConfigRegister;
56: u_int CpuStatusRegister;
57: u_int CpuExternalCacheOn; /* R5K, RM7K */
58: u_int CpuOnboardCacheOn; /* RM7K */
59:
60: int cpu_is_rm7k = 0;
61:
62: struct cfattach cpu_ca = {
63: sizeof(struct device), cpumatch, cpuattach
64: };
65: struct cfdriver cpu_cd = {
66: NULL, "cpu", DV_DULL, NULL, 0
67: };
68:
69: int
70: cpumatch(struct device *parent, void *match, void *aux)
71: {
72: struct cfdata *cf = match;
73: struct confargs *ca = aux;
74:
75: /* make sure that we're looking for a CPU. */
76: if (strcmp(ca->ca_name, cpu_cd.cd_name) != 0)
77: return 0;
78: if (cf->cf_unit >= MAX_CPUS)
79: return 0;
80:
81: return 20; /* Make CPU probe first */
82: }
83:
84: void
85: cpuattach(struct device *parent, struct device *dev, void *aux)
86: {
87: int cpuno = dev->dv_unit;
88:
89: printf(": ");
90:
91: switch (sys_config.cpu[cpuno].type) {
92: case MIPS_R4000:
93: if (CpuPrimaryInstCacheSize == 16384)
94: printf("MIPS R4400 CPU");
95: else
96: printf("MIPS R4000 CPU");
97: break;
98: case MIPS_R5000:
99: printf("MIPS R5000 CPU");
100: break;
101: case MIPS_R10000:
102: printf("MIPS R10000 CPU");
103: break;
104: case MIPS_R12000:
105: printf("MIPS R12000 CPU");
106: break;
107: case MIPS_R14000:
108: printf("MIPS R14000 CPU");
109: break;
110: case MIPS_R4200:
111: printf("NEC VR4200 CPU (ICE)");
112: break;
113: case MIPS_R4300:
114: printf("NEC VR4300 CPU");
115: break;
116: case MIPS_R4100:
117: printf("NEC VR41xx CPU");
118: break;
119: case MIPS_R4600:
120: printf("QED R4600 Orion CPU");
121: break;
122: case MIPS_R4700:
123: printf("QED R4700 Orion CPU");
124: break;
125: case MIPS_RM52X0:
126: printf("PMC-Sierra RM52X0 CPU");
127: break;
128: case MIPS_RM7000:
129: if (sys_config.cpu[cpuno].vers_maj < 2)
130: printf("PMC-Sierra RM7000 CPU");
131: else
132: printf("PMC-Sierra RM7000A CPU");
133: cpu_is_rm7k++;
134: break;
135: case MIPS_RM9000:
136: printf("PMC-Sierra RM9000 CPU");
137: break;
138: default:
139: printf("Unknown CPU type (0x%x)",sys_config.cpu[cpuno].type);
140: break;
141: }
142: printf(" rev %d.%d %d MHz with ", sys_config.cpu[cpuno].vers_maj,
143: sys_config.cpu[cpuno].vers_min,
144: sys_config.cpu[cpuno].clock / 1000000);
145:
146: switch (sys_config.cpu[cpuno].fptype) {
147: case MIPS_SOFT:
148: printf("Software emulation float");
149: break;
150: case MIPS_R4000:
151: printf("R4010 FPC");
152: break;
153: case MIPS_R10000:
154: printf("R10000 FPU");
155: break;
156: case MIPS_R12000:
157: printf("R12000 FPU");
158: break;
159: case MIPS_R14000:
160: printf("R14000 FPU");
161: break;
162: case MIPS_R4200:
163: printf("VR4200 FPC (ICE)");
164: break;
165: case MIPS_R4600:
166: printf("R4600 Orion FPC");
167: break;
168: case MIPS_R4700:
169: printf("R4700 Orion FPC");
170: break;
171: case MIPS_R5000:
172: printf("R5000 based FPC");
173: break;
174: case MIPS_RM52X0:
175: printf("RM52X0 FPC");
176: break;
177: case MIPS_RM7000:
178: printf("RM7000 FPC");
179: break;
180: case MIPS_RM9000:
181: printf("RM9000 FPC");
182: break;
183: default:
184: printf("Unknown FPU type (0x%x)", sys_config.cpu[cpuno].fptype);
185: break;
186: }
187: printf(" rev %d.%d\n", sys_config.cpu[cpuno].fpvers_maj,
188: sys_config.cpu[cpuno].fpvers_min);
189:
190: printf("cpu%d: cache L1-I %dKB", cpuno, CpuPrimaryInstCacheSize / 1024);
191: printf(" D %dKB ", CpuPrimaryDataCacheSize / 1024);
192:
193: switch (CpuNWayCache) {
194: case 2:
195: printf("2 way");
196: break;
197: case 4:
198: printf("4 way");
199: break;
200: default:
201: printf("1 way");
202: break;
203: }
204:
205: if (CpuSecondaryCacheSize != 0) {
206: switch (sys_config.cpu[cpuno].type) {
207: case MIPS_R10000:
208: case MIPS_R12000:
209: case MIPS_R14000:
210: printf(", L2 %dKB 2 way", CpuSecondaryCacheSize / 1024);
211: break;
212: case MIPS_RM7000:
213: case MIPS_RM9000:
214: printf(", L2 %dKB 4 way", CpuSecondaryCacheSize / 1024);
215: break;
216: default:
217: printf(", L2 %dKB direct", CpuSecondaryCacheSize / 1024);
218: break;
219: }
220: }
221: if (CpuTertiaryCacheSize != 0)
222: printf(", L3 %dKB direct", CpuTertiaryCacheSize / 1024);
223: printf("\n");
224:
225: #ifdef DEBUG
226: printf("cpu%d: Setsize %d:%d\n", cpuno,
227: CpuPrimaryInstSetSize, CpuPrimaryDataSetSize);
228: printf("cpu%d: Alias mask 0x%x\n", cpuno, CpuCacheAliasMask);
229: printf("cpu%d: Config Register %x\n", cpuno, CpuConfigRegister);
230: printf("cpu%d: Cache type %x\n", cpuno, CpuCacheType);
231: if (sys_config.cpu[cpuno].fptype == MIPS_RM7000) {
232: u_int tmp = CpuConfigRegister;
233:
234: printf("cpu%d: ", cpuno);
235: printf("K0 = %1d ",0x7 & tmp);
236: printf("SE = %1d ",0x1 & (tmp>>3));
237: printf("DB = %1d ",0x1 & (tmp>>4));
238: printf("IB = %1d\n",0x1 & (tmp>>5));
239: printf("cpu%d: ", cpuno);
240: printf("DC = %1d ",0x7 & (tmp>>6));
241: printf("IC = %1d ",0x7 & (tmp>>9));
242: printf("TE = %1d ",0x1 & (tmp>>12));
243: printf("EB = %1d\n",0x1 & (tmp>>13));
244: printf("cpu%d: ", cpuno);
245: printf("EM = %1d ",0x1 & (tmp>>14));
246: printf("BE = %1d ",0x1 & (tmp>>15));
247: printf("TC = %1d ",0x1 & (tmp>>17));
248: printf("EW = %1d\n",0x3 & (tmp>>18));
249: printf("cpu%d: ", cpuno);
250: printf("TS = %1d ",0x3 & (tmp>>20));
251: printf("EP = %1d ",0xf & (tmp>>24));
252: printf("EC = %1d ",0x7 & (tmp>>28));
253: printf("SC = %1d\n",0x1 & (tmp>>31));
254: }
255: printf("cpu%d: Status Register %x\n", cpuno, CpuStatusRegister);
256: #endif
257: }
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