Annotation of sys/arch/mips64/mips64/cp0access.S, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: cp0access.S,v 1.7 2007/07/16 20:23:09 miod Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com)
! 5: *
! 6: * Redistribution and use in source and binary forms, with or without
! 7: * modification, are permitted provided that the following conditions
! 8: * are met:
! 9: * 1. Redistributions of source code must retain the above copyright
! 10: * notice, this list of conditions and the following disclaimer.
! 11: * 2. Redistributions in binary form must reproduce the above copyright
! 12: * notice, this list of conditions and the following disclaimer in the
! 13: * documentation and/or other materials provided with the distribution.
! 14: *
! 15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
! 16: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 17: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 18: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
! 19: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 20: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 21: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 22: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 23: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 24: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 25: * SUCH DAMAGE.
! 26: *
! 27: */
! 28:
! 29: /*
! 30: * Low level code to manage processor specific registers.
! 31: */
! 32:
! 33: #include <sys/errno.h>
! 34: #include <sys/syscall.h>
! 35:
! 36: #include <machine/param.h>
! 37: #include <machine/psl.h>
! 38: #include <machine/asm.h>
! 39: #include <machine/cpu.h>
! 40: #include <machine/regnum.h>
! 41: #include <machine/pte.h>
! 42:
! 43: #include "assym.h"
! 44:
! 45: .set noreorder # Noreorder is default style!
! 46:
! 47: /*
! 48: * Set/clear software interrupt.
! 49: */
! 50:
! 51: LEAF(setsoftintr0, 0)
! 52: mfc0 v0, COP_0_CAUSE_REG # read cause register
! 53: nop
! 54: or v0, v0, SOFT_INT_MASK_0 # set soft clock interrupt
! 55: mtc0 v0, COP_0_CAUSE_REG # save it
! 56: j ra
! 57: nop
! 58: END(setsoftintr0)
! 59:
! 60: LEAF(clearsoftintr0, 0)
! 61: mfc0 v0, COP_0_CAUSE_REG # read cause register
! 62: nop
! 63: and v0, v0, ~SOFT_INT_MASK_0 # clear soft clock interrupt
! 64: mtc0 v0, COP_0_CAUSE_REG # save it
! 65: j ra
! 66: nop
! 67: END(clearsoftintr0)
! 68:
! 69: LEAF(setsoftintr1, 0)
! 70: mfc0 v0, COP_0_CAUSE_REG # read cause register
! 71: nop
! 72: or v0, v0, SOFT_INT_MASK_1 # set soft net interrupt
! 73: mtc0 v0, COP_0_CAUSE_REG # save it
! 74: j ra
! 75: nop
! 76: END(setsoftintr1)
! 77:
! 78: LEAF(clearsoftintr1, 0)
! 79: mfc0 v0, COP_0_CAUSE_REG # read cause register
! 80: nop
! 81: and v0, v0, ~SOFT_INT_MASK_1 # clear soft net interrupt
! 82: mtc0 v0, COP_0_CAUSE_REG # save it
! 83: j ra
! 84: nop
! 85: END(clearsoftintr1)
! 86:
! 87: /*
! 88: * Set/change interrupt priority routines.
! 89: * These routines return the previous state.
! 90: */
! 91:
! 92: LEAF(enableintr, 0)
! 93: mfc0 v0, COP_0_STATUS_REG # read status register
! 94: nop
! 95: or v1, v0, SR_INT_ENAB
! 96: mtc0 v1, COP_0_STATUS_REG # enable all interrupts
! 97: ITLBNOPFIX
! 98: j ra
! 99: nop
! 100: END(enableintr)
! 101:
! 102: LEAF(disableintr, 0)
! 103: mfc0 v0, COP_0_STATUS_REG # read status register
! 104: nop
! 105: and v1, v0, ~SR_INT_ENAB
! 106: mtc0 v1, COP_0_STATUS_REG # disable all interrupts
! 107: ITLBNOPFIX # Propagate new status
! 108: j ra
! 109: nop
! 110: END(disableintr)
! 111:
! 112: LEAF(updateimask, 0)
! 113: lw t0, idle_mask
! 114: not a0, a0 # 1 means masked so invert.
! 115: and a0, t0 # never upgrade to higher than max
! 116: #ifndef IMASK_EXTERNAL
! 117: cfc0 v0, COP_0_ICR
! 118: li v1, ~IC_INT_MASK
! 119: and v1, v0
! 120: sll v0, a0, 8
! 121: and v0, IC_INT_MASK
! 122: and v0, a0, IC_INT_MASK
! 123: or v1, v0
! 124: ctc0 v1, COP_0_ICR
! 125: #endif
! 126: mfc0 v0, COP_0_STATUS_REG
! 127: li v1, ~SR_INT_MASK
! 128: and v1, v0
! 129: and v0, a0, SR_INT_MASK
! 130: or v1, v0
! 131: mtc0 v1, COP_0_STATUS_REG
! 132: ITLBNOPFIX
! 133: jr ra
! 134: move v0, v1
! 135: END(updateimask)
! 136:
! 137: LEAF(setsr, 0)
! 138: mtc0 a0, COP_0_STATUS_REG
! 139: ITLBNOPFIX
! 140: jr ra
! 141: move v0, a0
! 142: END(setsr)
! 143:
! 144: LEAF(getsr, 0)
! 145: mfc0 v0, COP_0_STATUS_REG
! 146: jr ra
! 147: nop
! 148: END(getsr)
! 149:
! 150: LEAF(cp0_get_prid, 0)
! 151: mfc0 v0, COP_0_PRID
! 152: j ra
! 153: nop
! 154: END(cp0_get_prid)
! 155:
! 156: LEAF(cp0_get_count, 0)
! 157: mfc0 v0, COP_0_COUNT
! 158: j ra
! 159: nop
! 160: END(cp0_get_count)
! 161:
! 162: LEAF(cp0_set_compare, 0)
! 163: mtc0 a0, COP_0_COMPARE
! 164: j ra
! 165: nop
! 166: END(cp0_set_compare)
! 167:
! 168: LEAF(cp0_getperfcount, 0)
! 169: mfc0 v0, COP_0_PC_COUNT
! 170: nop; nop
! 171: j ra
! 172: nop
! 173: END(cp0_getperfcount)
! 174:
! 175: LEAF(cp0_setperfcount, 0)
! 176: mtc0 a0, COP_0_PC_COUNT
! 177: nop; nop
! 178: j ra
! 179: nop
! 180: END(cp0_setperfcount)
! 181:
! 182: LEAF(cp0_setperfctrl, 0)
! 183: mtc0 a0, COP_0_PC_CTRL
! 184: nop; nop
! 185: j ra
! 186: nop
! 187: END(cp0_setperfctrl)
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