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Annotation of sys/arch/mips64/include/rm7000.h, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: rm7000.h,v 1.2 2005/01/31 21:35:49 grange Exp $ */
                      2:
                      3: /*
                      4:  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
                      5:  *
                      6:  * Redistribution and use in source and binary forms, with or without
                      7:  * modification, are permitted provided that the following conditions
                      8:  * are met:
                      9:  * 1. Redistributions of source code must retain the above copyright
                     10:  *    notice, this list of conditions and the following disclaimer.
                     11:  * 2. Redistributions in binary form must reproduce the above copyright
                     12:  *    notice, this list of conditions and the following disclaimer in the
                     13:  *    documentation and/or other materials provided with the distribution.
                     14:  *
                     15:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
                     16:  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
                     17:  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
                     18:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
                     19:  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
                     20:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
                     21:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
                     22:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
                     23:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
                     24:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
                     25:  * SUCH DAMAGE.
                     26:  *
                     27:  */
                     28:
                     29: #ifndef _MIPS64_RM7000_H_
                     30: #define _MIPS64_RM7000_H_
                     31:
                     32: /*
                     33:  *  QED RM7000 specific defines.
                     34:  */
                     35:
                     36: /*
                     37:  *  Performance counters.
                     38:  */
                     39:
                     40: #define        PCNT_SRC_CLOCKS         0x00    /* Clock cycles */
                     41: #define        PCNT_SRC_INSTR          0x01    /* Total instructions issued */
                     42: #define        PCNT_SRC_FPINSTR        0x02    /* Float instructions issued */
                     43: #define        PCNT_SRC_IINSTR         0x03    /* Integer instructions issued */
                     44: #define        PCNT_SRC_LOAD           0x04    /* Load instructions issued */
                     45: #define        PCNT_SRC_STORE          0x05    /* Store instructions issued */
                     46: #define        PCNT_SRC_DUAL           0x06    /* Dual issued pairs */
                     47: #define        PCNT_SRC_BRPREF         0x07    /* Branch prefetches */
                     48: #define        PCNT_SRC_EXTMISS        0x08    /* External cache misses */
                     49: #define        PCNT_SRC_STALL          0x09    /* Stall cycles */
                     50: #define        PCNT_SRC_SECMISS        0x0a    /* Secondary cache misses */
                     51: #define        PCNT_SRC_INSMISS        0x0b    /* Instruction cache misses */
                     52: #define        PCNT_SRC_DTAMISS        0x0c    /* Data cache misses */
                     53: #define        PCNT_SRC_DTLBMISS       0x0d    /* Data TLB misses */
                     54: #define        PCNT_SRC_ITLBMISS       0x0e    /* Instruction TLB misses */
                     55: #define        PCNT_SRC_JTLBIMISS      0x0f    /* Joint TLB instruction misses */
                     56: #define        PCNT_SRC_JTLBDMISS      0x10    /* Joint TLB data misses */
                     57: #define        PCNT_SRC_BRTAKEN        0x11    /* Branches taken */
                     58: #define        PCNT_SRC_BRISSUED       0x12    /* Branches issued */
                     59: #define        PCNT_SRC_SECWBACK       0x13    /* Secondary cache writebacks */
                     60: #define        PCNT_SRC_PRIWBACK       0x14    /* Primary cache writebacks */
                     61: #define        PCNT_SRC_DCSTALL        0x15    /* Dcache miss stall cycles */
                     62: #define        PCNT_SRC_MISS           0x16    /* Cache misses */
                     63: #define        PCNT_SRC_FPEXC          0x17    /* FP possible execption cycles */
                     64: #define        PCNT_SRC_MULSLIP        0x18    /* Slip cycles due to mult. busy */
                     65: #define        PCNT_SRC_CP0SLIP        0x19    /* CP0 Slip cycles */
                     66: #define        PCNT_SRC_LDSLIP         0x1a    /* Slip cycles  due to pend. non-b ld */
                     67: #define        PCNT_SRC_WBFULL         0x1b    /* Write buffer full stall cycles  */
                     68: #define        PCNT_SRC_CISTALL        0x1c    /* Cache instruction stall cycles  */
                     69: #define        PCNT_SRC_MULSTALL       0x1d    /* Multiplier stall cycles  */
                     70: #define        PCNT_SRC_ELDSTALL       0x1d    /* Excepion stall due to non-b ld */
                     71: #define        PCNT_SRC_MAX            0x1d    /* Maximum PCNT select code */
                     72:
                     73: /*
                     74:  *  Counter control bits.
                     75:  */
                     76:
                     77: #define        PCNT_CE                 0x0400  /* Count enable */
                     78: #define        PCNT_UM                 0x0200  /* Count in User mode */
                     79: #define        PCNT_KM                 0x0100  /* Count in kernel mode */
                     80:
                     81: /*
                     82:  *  Performance counter system call function codes.
                     83:  */
                     84: #define        PCNT_FNC_SELECT         0x0001  /* Select counter source */
                     85: #define        PCNT_FNC_READ           0x0002  /* Read current value of counter */
                     86:
                     87:
                     88: #ifdef _KERNEL
                     89: __BEGIN_DECLS
                     90: int    rm7k_perfcntr(int, long, long, long);
                     91: void   rm7k_perfintr(struct trap_frame *);
                     92: int    rm7k_watchintr(struct trap_frame *);
                     93: void   cp0_setperfcount(int);
                     94: void   cp0_setperfctrl(int);
                     95: int    cp0_getperfcount(void);
                     96: __END_DECLS
                     97: #endif /* _KERNEL */
                     98:
                     99: #endif /* _MIPS64_RM7000_H_ */