Annotation of sys/arch/mips64/include/cpustate.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cpustate.h,v 1.6 2004/10/20 12:49:15 pefo Exp $ */
2:
3: /*
4: * Copyright (c) 2002-2003 Opsycon AB (www.opsycon.se / www.opsycon.com)
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: *
15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25: * SUCH DAMAGE.
26: *
27: */
28:
29: #define KERN_REG_SIZE (NUMSAVEREGS * REGSZ)
30: #define KERN_EXC_FRAME_SIZE (CF_SZ + KERN_REG_SIZE + 16)
31:
32: #define SAVE_REG(reg, offs, base, bo) \
33: REG_S reg, bo + (REGSZ * offs) (base)
34:
35: #define RESTORE_REG(reg, offs, base, bo) \
36: REG_L reg, bo + (REGSZ * offs) (base)
37:
38: /*
39: * This macro saves the 'scratch' cpu state on stack.
40: * Macros are generic so no 'special' instructions!
41: * a0 will have a pointer to the 'frame' on return.
42: * a1 will have saved STATUS_REG on return.
43: * a3 will have the exception pc on 'return'.
44: * No traps, no interrupts if frame = k1 or k0!
45: * Temp regs are saved with their register number so
46: * branch emulation etc works properly.
47: */
48: #define SAVE_CPU(frame, bo) \
49: SAVE_REG(AT, AST, frame, bo) ;\
50: SAVE_REG(v0, V0, frame, bo) ;\
51: SAVE_REG(v1, V1, frame, bo) ;\
52: SAVE_REG(a0, A0, frame, bo) ;\
53: SAVE_REG(a1, A1, frame, bo) ;\
54: SAVE_REG(a2, A2, frame, bo) ;\
55: SAVE_REG(a3, A3, frame, bo) ;\
56: SAVE_REG($8, T0, frame, bo) ;\
57: SAVE_REG($9, T1, frame, bo) ;\
58: SAVE_REG($10, T2, frame, bo) ;\
59: SAVE_REG($11, T3, frame, bo) ;\
60: SAVE_REG($12, T4, frame, bo) ;\
61: SAVE_REG($13, T5, frame, bo) ;\
62: SAVE_REG($14, T6, frame, bo) ;\
63: SAVE_REG($15, T7, frame, bo) ;\
64: SAVE_REG(t8, T8, frame, bo) ;\
65: SAVE_REG(t9, T9, frame, bo) ;\
66: SAVE_REG(gp, GP, frame, bo) ;\
67: SAVE_REG(ra, RA, frame, bo) ;\
68: mflo v0 ;\
69: mfhi v1 ;\
70: mfc0 a0, COP_0_CAUSE_REG ;\
71: mfc0 a1, COP_0_STATUS_REG ;\
72: dmfc0 a2, COP_0_BAD_VADDR ;\
73: dmfc0 a3, COP_0_EXC_PC ;\
74: SAVE_REG(v0, MULLO, frame, bo) ;\
75: SAVE_REG(v1, MULHI, frame, bo) ;\
76: SAVE_REG(a0, CAUSE, frame, bo) ;\
77: SAVE_REG(a1, SR, frame, bo) ;\
78: SAVE_REG(a2, BADVADDR, frame, bo) ;\
79: SAVE_REG(a3, PC, frame, bo) ;\
80: SAVE_REG(sp, SP, frame, bo) ;\
81: PTR_ADDU a0, frame, bo ;\
82: lw a2, cpl ;\
83: SAVE_REG(a2, CPL, frame, bo)
84:
85: /*
86: * Save 'callee save' registers in frame to aid DDB.
87: */
88: #define SAVE_CPU_SREG(frame, bo) \
89: SAVE_REG(s0, S0, frame, bo) ;\
90: SAVE_REG(s1, S1, frame, bo) ;\
91: SAVE_REG(s2, S2, frame, bo) ;\
92: SAVE_REG(s3, S3, frame, bo) ;\
93: SAVE_REG(s4, S4, frame, bo) ;\
94: SAVE_REG(s5, S5, frame, bo) ;\
95: SAVE_REG(s6, S6, frame, bo) ;\
96: SAVE_REG(s7, S7, frame, bo) ;\
97: SAVE_REG(s8, S8, frame, bo)
98:
99: /*
100: * Restore cpu state. When called a0 = EXC_PC.
101: */
102: #define RESTORE_CPU(frame, bo) \
103: RESTORE_REG(t1, SR, frame, bo) ;\
104: RESTORE_REG(t2, MULLO, frame, bo) ;\
105: RESTORE_REG(t3, MULHI, frame, bo) ;\
106: mtc0 t1, COP_0_STATUS_REG ;\
107: mtlo t2 ;\
108: mthi t3 ;\
109: dmtc0 a0, COP_0_EXC_PC ;\
110: RESTORE_REG(AT, AST, frame, bo) ;\
111: RESTORE_REG(v0, V0, frame, bo) ;\
112: RESTORE_REG(v1, V1, frame, bo) ;\
113: RESTORE_REG(a0, A0, frame, bo) ;\
114: RESTORE_REG(a1, A1, frame, bo) ;\
115: RESTORE_REG(a2, A2, frame, bo) ;\
116: RESTORE_REG(a3, A3, frame, bo) ;\
117: RESTORE_REG($8, T0, frame, bo) ;\
118: RESTORE_REG($9, T1, frame, bo) ;\
119: RESTORE_REG($10, T2, frame, bo) ;\
120: RESTORE_REG($11, T3, frame, bo) ;\
121: RESTORE_REG($12, T4, frame, bo) ;\
122: RESTORE_REG($13, T5, frame, bo) ;\
123: RESTORE_REG($14, T6, frame, bo) ;\
124: RESTORE_REG($15, T7, frame, bo) ;\
125: RESTORE_REG(t8, T8, frame, bo) ;\
126: RESTORE_REG(t9, T9, frame, bo) ;\
127: RESTORE_REG(gp, GP, frame, bo) ;\
128: RESTORE_REG(ra, RA, frame, bo)
129:
130: /*
131: * Restore 'callee save' registers
132: */
133: #define RESTORE_CPU_SREG(frame, bo) \
134: RESTORE_REG(s0, S0, frame, bo) ;\
135: RESTORE_REG(s1, S1, frame, bo) ;\
136: RESTORE_REG(s2, S2, frame, bo) ;\
137: RESTORE_REG(s3, S3, frame, bo) ;\
138: RESTORE_REG(s4, S4, frame, bo) ;\
139: RESTORE_REG(s5, S5, frame, bo) ;\
140: RESTORE_REG(s6, S6, frame, bo) ;\
141: RESTORE_REG(s7, S7, frame, bo) ;\
142: RESTORE_REG(s8, S8, frame, bo)
143:
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