Annotation of sys/arch/mips64/include/cpu.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cpu.h,v 1.20 2007/07/18 20:03:50 miod Exp $ */
2:
3: /*-
4: * Copyright (c) 1992, 1993
5: * The Regents of the University of California. All rights reserved.
6: *
7: * This code is derived from software contributed to Berkeley by
8: * Ralph Campbell and Rick Macklem.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: *
34: * Copyright (C) 1989 Digital Equipment Corporation.
35: * Permission to use, copy, modify, and distribute this software and
36: * its documentation for any purpose and without fee is hereby granted,
37: * provided that the above copyright notice appears in all copies.
38: * Digital Equipment Corporation makes no representations about the
39: * suitability of this software for any purpose. It is provided "as is"
40: * without express or implied warranty.
41: *
42: * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
43: */
44:
45: #ifndef _MIPS_CPU_H_
46: #define _MIPS_CPU_H_
47:
48: #include <machine/psl.h>
49:
50: #ifdef __LP64__
51: #define KSEG0_BASE 0xffffffff80000000
52: #define KSEG1_BASE 0xffffffffa0000000
53: #define KSSEG_BASE 0xffffffffc0000000
54: #define KSEG3_BASE 0xffffffffe0000000
55: #else
56: #define KSEG0_BASE 0x80000000
57: #define KSEG1_BASE 0xa0000000
58: #define KSSEG_BASE 0xc0000000
59: #define KSEG3_BASE 0xe0000000
60: #endif
61: #define KSEG_SIZE 0x20000000
62:
63: #define KSEG0_TO_PHYS(x) ((u_long)(x) & 0x1fffffff)
64: #define KSEG1_TO_PHYS(x) ((u_long)(x) & 0x1fffffff)
65: #define PHYS_TO_KSEG0(x) ((u_long)(x) | KSEG0_BASE)
66: #define PHYS_TO_KSEG1(x) ((u_long)(x) | KSEG1_BASE)
67: #define PHYS_TO_KSEG3(x) ((u_long)(x) | KSEG3_BASE)
68:
69: /*
70: * Cache Coherency Attributes
71: * We only list values common to r4k and r5k.
72: */
73: #if !defined(_LOCORE)
74: #define CCA_NC 2UL /* uncached, write-around */
75: #define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */
76: #endif
77:
78: #ifdef __LP64__
79: #define XKPHYS_BASE 0x8000000000000000UL
80: #define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL)
81: #define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | (c) << 59)
82: #define IS_XKPHYS(va) (((va) >> 62) == 2)
83: #define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07)
84: #endif
85:
86: #ifdef _KERNEL
87:
88: /*
89: * Status register.
90: */
91: #define SR_XX 0x80000000
92: #define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */
93: #define SR_COP_0_BIT 0x10000000
94: #define SR_COP_1_BIT 0x20000000
95: #define SR_RP 0x08000000
96: #define SR_FR_32 0x04000000
97: #define SR_RE 0x02000000
98: #define SR_DSD 0x01000000 /* Only on R12000 */
99: #define SR_BOOT_EXC_VEC 0x00400000
100: #define SR_TLB_SHUTDOWN 0x00200000
101: #define SR_SOFT_RESET 0x00100000
102: #define SR_DIAG_CH 0x00040000
103: #define SR_DIAG_CE 0x00020000
104: #define SR_DIAG_DE 0x00010000
105: #define SR_KX 0x00000080
106: #define SR_SX 0x00000040
107: #define SR_UX 0x00000020
108: #define SR_KSU_MASK 0x00000018
109: #define SR_KSU_USER 0x00000010
110: #define SR_KSU_SUPER 0x00000008
111: #define SR_KSU_KERNEL 0x00000000
112: #define SR_ERL 0x00000004
113: #define SR_EXL 0x00000002
114: #define SR_INT_ENAB 0x00000001
115:
116: #define SR_INT_MASK 0x0000ff00
117: #define SOFT_INT_MASK_0 0x00000100
118: #define SOFT_INT_MASK_1 0x00000200
119: #define SR_INT_MASK_0 0x00000400
120: #define SR_INT_MASK_1 0x00000800
121: #define SR_INT_MASK_2 0x00001000
122: #define SR_INT_MASK_3 0x00002000
123: #define SR_INT_MASK_4 0x00004000
124: #define SR_INT_MASK_5 0x00008000
125: /*
126: * Interrupt control register in RM7000. Expansion of interrupts.
127: */
128: #define IC_INT_MASK 0x00003f00 /* Two msb reserved */
129: #define IC_INT_MASK_6 0x00000100
130: #define IC_INT_MASK_7 0x00000200
131: #define IC_INT_MASK_8 0x00000400
132: #define IC_INT_MASK_9 0x00000800
133: #define IC_INT_TIMR 0x00001000 /* 12 Timer */
134: #define IC_INT_PERF 0x00002000 /* 13 Performance counter */
135: #define IC_INT_TE 0x00000080 /* Timer on INT11 */
136:
137: #define ALL_INT_MASK ((IC_INT_MASK << 8) | SR_INT_MASK)
138: #define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1)
139: #define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK)
140:
141:
142: /*
143: * The bits in the cause register.
144: *
145: * CR_BR_DELAY Exception happened in branch delay slot.
146: * CR_COP_ERR Coprocessor error.
147: * CR_IP Interrupt pending bits defined below.
148: * CR_EXC_CODE The exception type (see exception codes below).
149: */
150: #define CR_BR_DELAY 0x80000000
151: #define CR_COP_ERR 0x30000000
152: #define CR_EXC_CODE 0x0000007c
153: #define CR_EXC_CODE_SHIFT 2
154: #define CR_IPEND 0x003fff00
155: #define CR_INT_SOFT0 0x00000100
156: #define CR_INT_SOFT1 0x00000200
157: #define CR_INT_0 0x00000400
158: #define CR_INT_1 0x00000800
159: #define CR_INT_2 0x00001000
160: #define CR_INT_3 0x00002000
161: #define CR_INT_4 0x00004000
162: #define CR_INT_5 0x00008000
163: /* Following on RM7000 */
164: #define CR_INT_6 0x00010000
165: #define CR_INT_7 0x00020000
166: #define CR_INT_8 0x00040000
167: #define CR_INT_9 0x00080000
168: #define CR_INT_HARD 0x000ffc00
169: #define CR_INT_TIMR 0x00100000 /* 12 Timer */
170: #define CR_INT_PERF 0x00200000 /* 13 Performance counter */
171:
172: /*
173: * The bits in the context register.
174: */
175: #define CNTXT_PTE_BASE 0xff800000
176: #define CNTXT_BAD_VPN2 0x007ffff0
177:
178: /*
179: * Location of exception vectors.
180: */
181: #define RESET_EXC_VEC (KSEG0_BASE + 0x3fc00000)
182: #define TLB_MISS_EXC_VEC (KSEG0_BASE + 0x00000000)
183: #define XTLB_MISS_EXC_VEC (KSEG0_BASE + 0x00000080)
184: #define CACHE_ERR_EXC_VEC (KSEG0_BASE + 0x00000100)
185: #define GEN_EXC_VEC (KSEG0_BASE + 0x00000180)
186:
187: /*
188: * Coprocessor 0 registers:
189: */
190: #define COP_0_TLB_INDEX $0
191: #define COP_0_TLB_RANDOM $1
192: #define COP_0_TLB_LO0 $2
193: #define COP_0_TLB_LO1 $3
194: #define COP_0_TLB_CONTEXT $4
195: #define COP_0_TLB_PG_MASK $5
196: #define COP_0_TLB_WIRED $6
197: #define COP_0_BAD_VADDR $8
198: #define COP_0_COUNT $9
199: #define COP_0_TLB_HI $10
200: #define COP_0_COMPARE $11
201: #define COP_0_STATUS_REG $12
202: #define COP_0_CAUSE_REG $13
203: #define COP_0_EXC_PC $14
204: #define COP_0_PRID $15
205: #define COP_0_CONFIG $16
206: #define COP_0_LLADDR $17
207: #define COP_0_WATCH_LO $18
208: #define COP_0_WATCH_HI $19
209: #define COP_0_TLB_XCONTEXT $20
210: #define COP_0_ECC $26
211: #define COP_0_CACHE_ERR $27
212: #define COP_0_TAG_LO $28
213: #define COP_0_TAG_HI $29
214: #define COP_0_ERROR_PC $30
215:
216: /*
217: * RM7000 specific
218: */
219: #define COP_0_WATCH_1 $18
220: #define COP_0_WATCH_2 $19
221: #define COP_0_WATCH_M $24
222: #define COP_0_PC_COUNT $25
223: #define COP_0_PC_CTRL $22
224:
225: #define COP_0_ICR $20 /* Use cfc0/ctc0 to access */
226:
227: /*
228: * Values for the code field in a break instruction.
229: */
230: #define BREAK_INSTR 0x0000000d
231: #define BREAK_VAL_MASK 0x03ff0000
232: #define BREAK_VAL_SHIFT 16
233: #define BREAK_KDB_VAL 512
234: #define BREAK_SSTEP_VAL 513
235: #define BREAK_BRKPT_VAL 514
236: #define BREAK_SOVER_VAL 515
237: #define BREAK_DDB_VAL 516
238: #define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT))
239: #define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT))
240: #define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT))
241: #define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT))
242: #define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT))
243:
244: /*
245: * Mininum and maximum cache sizes.
246: */
247: #define MIN_CACHE_SIZE (16 * 1024)
248: #define MAX_CACHE_SIZE (256 * 1024)
249:
250: /*
251: * The floating point version and status registers.
252: */
253: #define FPC_ID $0
254: #define FPC_CSR $31
255:
256: /*
257: * The floating point coprocessor status register bits.
258: */
259: #define FPC_ROUNDING_BITS 0x00000003
260: #define FPC_ROUND_RN 0x00000000
261: #define FPC_ROUND_RZ 0x00000001
262: #define FPC_ROUND_RP 0x00000002
263: #define FPC_ROUND_RM 0x00000003
264: #define FPC_STICKY_BITS 0x0000007c
265: #define FPC_STICKY_INEXACT 0x00000004
266: #define FPC_STICKY_UNDERFLOW 0x00000008
267: #define FPC_STICKY_OVERFLOW 0x00000010
268: #define FPC_STICKY_DIV0 0x00000020
269: #define FPC_STICKY_INVALID 0x00000040
270: #define FPC_ENABLE_BITS 0x00000f80
271: #define FPC_ENABLE_INEXACT 0x00000080
272: #define FPC_ENABLE_UNDERFLOW 0x00000100
273: #define FPC_ENABLE_OVERFLOW 0x00000200
274: #define FPC_ENABLE_DIV0 0x00000400
275: #define FPC_ENABLE_INVALID 0x00000800
276: #define FPC_EXCEPTION_BITS 0x0003f000
277: #define FPC_EXCEPTION_INEXACT 0x00001000
278: #define FPC_EXCEPTION_UNDERFLOW 0x00002000
279: #define FPC_EXCEPTION_OVERFLOW 0x00004000
280: #define FPC_EXCEPTION_DIV0 0x00008000
281: #define FPC_EXCEPTION_INVALID 0x00010000
282: #define FPC_EXCEPTION_UNIMPL 0x00020000
283: #define FPC_COND_BIT 0x00800000
284: #define FPC_FLUSH_BIT 0x01000000
285: #define FPC_MBZ_BITS 0xfe7c0000
286:
287: /*
288: * Constants to determine if have a floating point instruction.
289: */
290: #define OPCODE_SHIFT 26
291: #define OPCODE_C1 0x11
292:
293: /*
294: * The low part of the TLB entry.
295: */
296: #define VMTLB_PF_NUM 0x3fffffc0
297: #define VMTLB_ATTR_MASK 0x00000038
298: #define VMTLB_MOD_BIT 0x00000004
299: #define VMTLB_VALID_BIT 0x00000002
300: #define VMTLB_GLOBAL_BIT 0x00000001
301:
302: #define VMTLB_PHYS_PAGE_SHIFT 6
303:
304: /*
305: * The high part of the TLB entry.
306: */
307: #define VMTLB_VIRT_PAGE_NUM 0xffffe000
308: #define VMTLB_PID 0x000000ff
309: #define VMTLB_PID_SHIFT 0
310: #define VMTLB_VIRT_PAGE_SHIFT 12
311:
312: /*
313: * The number of process id entries.
314: */
315: #define VMNUM_PIDS 256
316:
317: /*
318: * TLB probe return codes.
319: */
320: #define VMTLB_NOT_FOUND 0
321: #define VMTLB_FOUND 1
322: #define VMTLB_FOUND_WITH_PATCH 2
323: #define VMTLB_PROBE_ERROR 3
324:
325: /*
326: * Exported definitions unique to mips cpu support.
327: */
328:
329: /*
330: * definitions of cpu-dependent requirements
331: * referenced in generic code
332: */
333: #define cpu_wait(p) /* nothing */
334:
335: #ifndef _LOCORE
336:
337: #include <sys/sched.h>
338:
339: struct cpu_info {
340: struct schedstate_percpu ci_schedstate;
341:
342: struct proc *ci_curproc;
343: };
344:
345: extern struct cpu_info cpu_info_primary;
346:
347: #define curcpu() (&cpu_info_primary)
348:
349: #define CPU_IS_PRIMARY(ci) 1
350: #define CPU_INFO_ITERATOR int
351: #define CPU_INFO_FOREACH(cii, ci) \
352: for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
353:
354: #define cpu_number() 0
355:
356: #include <machine/frame.h>
357: /*
358: * Arguments to hardclock and gatherstats encapsulate the previous
359: * machine state in an opaque clockframe.
360: */
361: extern int int_nest_cntr;
362: #define clockframe trap_frame /* Use normal trap frame */
363:
364: #define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER)
365: #define CLKF_PC(framep) ((framep)->pc)
366: #define CLKF_INTR(framep) (int_nest_cntr > 0)
367:
368: /*
369: * This is used during profiling to integrate system time.
370: */
371: #define PROC_PC(p) ((p)->p_md.md_regs->pc)
372:
373: /*
374: * Preempt the current process if in interrupt from user mode,
375: * or after the current trap/syscall if in system mode.
376: */
377: #define need_resched(info) { want_resched = 1; aston(); }
378:
379: /*
380: * Give a profiling tick to the current process when the user profiling
381: * buffer pages are invalid. On the PICA, request an ast to send us
382: * through trap, marking the proc as needing a profiling tick.
383: */
384: #define need_proftick(p) aston()
385:
386: /*
387: * Notify the current process (p) that it has a signal pending,
388: * process as soon as possible.
389: */
390: #define signotify(p) aston()
391:
392: #define aston() (astpending = 1)
393:
394: extern int want_resched; /* resched() was called */
395:
396: #endif /* !_LOCORE */
397: #endif /* _KERNEL */
398:
399: /*
400: * CTL_MACHDEP definitions.
401: */
402: #define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */
403: #define CPU_MAXID 2 /* number of valid machdep ids */
404:
405: #define CTL_MACHDEP_NAMES { \
406: { 0, 0 }, \
407: { "allowaperture", CTLTYPE_INT }, \
408: }
409:
410: /*
411: * MIPS CPU types (cp_imp).
412: */
413: #define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
414: #define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
415: #define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
416: #define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
417: #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
418: #define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
419: #define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
420: #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
421: #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
422: #define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
423: #define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */
424: #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
425: #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
426: #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
427: #define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */
428: #define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */
429: #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
430: #define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
431: #define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */
432: #define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */
433: #define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */
434: #define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */
435:
436: /*
437: * MIPS FPU types. Only soft, rest is teh same as cpu type.
438: */
439: #define MIPS_SOFT 0x00 /* Software emulation ISA I */
440:
441:
442: #if defined(_KERNEL) && !defined(_LOCORE)
443:
444: extern u_int CpuPrimaryInstCacheSize;
445: extern u_int CpuPrimaryInstCacheLSize;
446: extern u_int CpuPrimaryInstSetSize;
447: extern u_int CpuPrimaryDataCacheSize;
448: extern u_int CpuPrimaryDataCacheLSize;
449: extern u_int CpuPrimaryDataSetSize;
450: extern u_int CpuCacheAliasMask;
451: extern u_int CpuSecondaryCacheSize;
452: extern u_int CpuTertiaryCacheSize;
453: extern u_int CpuNWayCache;
454: extern u_int CpuCacheType; /* R4K, R5K, RM7K */
455: extern u_int CpuConfigRegister;
456: extern u_int CpuStatusRegister;
457: extern u_int CpuExternalCacheOn; /* R5K, RM7K */
458: extern u_int CpuOnboardCacheOn; /* RM7K */
459:
460: struct tlb_entry;
461: struct user;
462:
463: void tlb_set_wired(int);
464: void tlb_set_pid(int);
465: u_int cp0_get_prid(void);
466: u_int cp1_get_prid(void);
467: u_int cp0_get_count(void);
468: void cp0_set_compare(u_int);
469:
470: /*
471: * Define soft selected cache functions.
472: */
473: #define Mips_SyncCache() (*(sys_config._SyncCache))()
474: #define Mips_InvalidateICache(a, l) \
475: (*(sys_config._InvalidateICache))((a), (l))
476: #define Mips_InvalidateICachePage(a) \
477: (*(sys_config._InvalidateICachePage))((a))
478: #define Mips_SyncDCachePage(a) \
479: (*(sys_config._SyncDCachePage))((a))
480: #define Mips_HitSyncDCache(a, l) \
481: (*(sys_config._HitSyncDCache))((a), (l))
482: #define Mips_IOSyncDCache(a, l, h) \
483: (*(sys_config._IOSyncDCache))((a), (l), (h))
484: #define Mips_HitInvalidateDCache(a, l) \
485: (*(sys_config._HitInvalidateDCache))((a), (l))
486:
487: int Mips5k_ConfigCache(void);
488: void Mips5k_SyncCache(void);
489: void Mips5k_InvalidateICache(vaddr_t, int);
490: void Mips5k_InvalidateICachePage(vaddr_t);
491: void Mips5k_SyncDCachePage(vaddr_t);
492: void Mips5k_HitSyncDCache(vaddr_t, int);
493: void Mips5k_IOSyncDCache(vaddr_t, int, int);
494: void Mips5k_HitInvalidateDCache(vaddr_t, int);
495:
496: int Mips10k_ConfigCache(void);
497: void Mips10k_SyncCache(void);
498: void Mips10k_InvalidateICache(vaddr_t, int);
499: void Mips10k_InvalidateICachePage(vaddr_t);
500: void Mips10k_SyncDCachePage(vaddr_t);
501: void Mips10k_HitSyncDCache(vaddr_t, int);
502: void Mips10k_IOSyncDCache(vaddr_t, int, int);
503: void Mips10k_HitInvalidateDCache(vaddr_t, int);
504:
505: void tlb_flush(int);
506: void tlb_flush_addr(vaddr_t);
507: void tlb_write_indexed(int, struct tlb_entry *);
508: int tlb_update(vaddr_t, unsigned);
509: void tlb_read(int, struct tlb_entry *);
510:
511: void savectx(struct user *, int);
512: void switch_exit(struct proc *);
513: void MipsSaveCurFPState(struct proc *);
514: void MipsSaveCurFPState16(struct proc *);
515:
516: extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */
517: extern u_int32_t cpu_counter_last; /* Last compare value loaded */
518:
519: /*
520: * Low level access routines to CPU registers
521: */
522:
523: void setsoftintr0(void);
524: void clearsoftintr0(void);
525: void setsoftintr1(void);
526: void clearsoftintr1(void);
527: u_int32_t enableintr(void);
528: u_int32_t disableintr(void);
529: u_int32_t updateimask(intrmask_t);
530: void setsr(u_int32_t);
531: u_int32_t getsr(void);
532:
533: #endif /* _KERNEL */
534: #endif /* !_MIPS_CPU_H_ */
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