Annotation of sys/arch/macppc/include/bus.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: bus.h,v 1.13 2007/02/07 03:20:37 dlg Exp $ */
2:
3: /*
4: * Copyright (c) 1997 Per Fogelstrom. All rights reserved.
5: * Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Christopher G. Demetriou
18: * for the NetBSD Project.
19: * 4. The name of the author may not be used to endorse or promote products
20: * derived from this software without specific prior written permission
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32: */
33:
34: #ifndef _MACHINE_BUS_H_
35: #define _MACHINE_BUS_H_
36:
37: #include <machine/pio.h>
38:
39: #ifdef __STDC__
40: #define CAT(a,b) a##b
41: #define CAT3(a,b,c) a##b##c
42: #else
43: #define CAT(a,b) a/**/b
44: #define CAT3(a,b,c) a/**/b/**/c
45: #endif
46:
47: /*
48: * Bus access types.
49: */
50: typedef u_long bus_addr_t;
51: typedef u_int32_t bus_size_t;
52: typedef u_int32_t bus_space_handle_t;
53: typedef struct ppc_bus_space *bus_space_tag_t;
54:
55: struct ppc_bus_space {
56: u_int32_t bus_base;
57: u_int32_t bus_size;
58: u_int8_t bus_io; /* IO or memory */
59: };
60: #define POWERPC_BUS_TAG_BASE(x) ((x)->bus_base)
61:
62: extern struct ppc_bus_space ppc_isa_io, ppc_isa_mem;
63:
64: /*
65: * Access methods for bus resources
66: */
67: int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
68: bus_size_t size, int cacheable, bus_space_handle_t *bshp);
69: void bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
70: bus_size_t size);
71: int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
72: bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
73: int bus_space_alloc(bus_space_tag_t tag, bus_addr_t rstart,
74: bus_addr_t rend, bus_size_t size, bus_size_t alignment,
75: bus_size_t boundary, int cacheable, bus_addr_t *addrp,
76: bus_space_handle_t *handlep);
77: void bus_space_free(bus_space_tag_t tag, bus_space_handle_t handle,
78: bus_size_t size);
79:
80: #define bus_space_read(n,m) \
81: static __inline CAT3(u_int,m,_t) \
82: CAT(bus_space_read_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
83: bus_addr_t ba) \
84: { \
85: return CAT3(in,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (ba))); \
86: }
87:
88: bus_space_read(1,8)
89: bus_space_read(2,16)
90: bus_space_read(4,32)
91:
92: #define bus_space_read_8 !!! bus_space_read_8 unimplemented !!!
93:
94: #define bus_space_write(n,m) \
95: static __inline void \
96: CAT(bus_space_write_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
97: bus_addr_t ba, CAT3(u_int,m,_t) x) \
98: { \
99: CAT3(out,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (ba)), x); \
100: }
101:
102: bus_space_write(1,8)
103: bus_space_write(2,16)
104: bus_space_write(4,32)
105:
106: #define bus_space_write_8 !!! bus_space_write_8 unimplemented !!!
107:
108: #define bus_space_read_multi(n, m) \
109: static __inline void \
110: CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
111: bus_size_t ba, CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
112: { \
113: while (cnt--) \
114: *buf++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
115: }
116:
117: bus_space_read_multi(1,8)
118: bus_space_read_multi(2,16)
119: bus_space_read_multi(4,32)
120:
121: #define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!!
122:
123:
124: #define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
125:
126: #define bus_space_write_multi(n, m) \
127: static __inline void \
128: CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
129: bus_size_t ba, const CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
130: { \
131: while (cnt--) \
132: CAT(bus_space_write_,n)(bst, bsh, ba, *buf++); \
133: }
134:
135: bus_space_write_multi(1,8)
136: bus_space_write_multi(2,16)
137: bus_space_write_multi(4,32)
138:
139: #define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
140:
141: /*
142: * void bus_space_read_region_N(bus_space_tag_t tag,
143: * bus_space_handle_t bsh, bus_size_t offset,
144: * u_intN_t *addr, size_t count);
145: *
146: * Read `count' 1, 2, 4, or 8 byte quantities from bus space
147: * described by tag/handle and starting at `offset' and copy into
148: * buffer provided.
149: */
150: #define __BA(t, h, o) ((void *)((h) + (o)))
151:
152: static __inline void
153: bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
154: bus_size_t offset, u_int8_t *addr, size_t count)
155: {
156: volatile u_int8_t *s = __BA(tag, bsh, offset);
157:
158: while (count--)
159: *addr++ = *s++;
160: __asm __volatile("eieio; sync");
161: }
162:
163: static __inline void
164: bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
165: bus_size_t offset, u_int16_t *addr, size_t count)
166: {
167: volatile u_int16_t *s = __BA(tag, bsh, offset);
168:
169: while (count--)
170: __asm __volatile("lhbrx %0, 0, %1" :
171: "=r"(*addr++) : "r"(s++));
172: __asm __volatile("eieio; sync");
173: }
174:
175: static __inline void
176: bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
177: bus_size_t offset, u_int32_t *addr, size_t count)
178: {
179: volatile u_int32_t *s = __BA(tag, bsh, offset);
180:
181: while (count--)
182: __asm __volatile("lwbrx %0, 0, %1" :
183: "=r"(*addr++) : "r"(s++));
184: __asm __volatile("eieio; sync");
185: }
186:
187: #if 0 /* Cause a link error for bus_space_read_region_8 */
188: #define bus_space_read_region_8 !!! unimplemented !!!
189: #endif
190:
191:
192: /*
193: * void bus_space_write_region_N(bus_space_tag_t tag,
194: * bus_space_handle_t bsh, bus_size_t offset,
195: * const u_intN_t *addr, size_t count);
196: *
197: * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
198: * to bus space described by tag/handle starting at `offset'.
199: */
200:
201: static __inline void
202: bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
203: bus_size_t offset, const u_int8_t *addr, size_t count)
204: {
205: volatile u_int8_t *d = __BA(tag, bsh, offset);
206:
207: while (count--)
208: *d++ = *addr++;
209: __asm __volatile("eieio; sync");
210: }
211:
212: static __inline void
213: bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
214: bus_size_t offset, const u_int16_t *addr, size_t count)
215: {
216: volatile u_int16_t *d = __BA(tag, bsh, offset);
217:
218: while (count--)
219: __asm __volatile("sthbrx %0, 0, %1" ::
220: "r"(*addr++), "r"(d++));
221: __asm __volatile("eieio; sync");
222: }
223:
224: static __inline void
225: bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
226: bus_size_t offset, const u_int32_t *addr, size_t count)
227: {
228: volatile u_int32_t *d = __BA(tag, bsh, offset);
229:
230: while (count--)
231: __asm __volatile("stwbrx %0, 0, %1" ::
232: "r"(*addr++), "r"(d++));
233: __asm __volatile("eieio; sync");
234: }
235:
236: #if 0
237: #define bus_space_write_region_8 !!! bus_space_write_region_8 unimplemented !!!
238: #endif
239:
240: /*
241: * void bus_space_read_raw_region_N(bus_space_tag_t tag,
242: * bus_space_handle_t bsh, bus_size_t offset,
243: * u_intN_t *addr, size_t count);
244: *
245: * Read `count' bytes from bus space described by tag/handle and starting
246: * at `offset' and copy into buffer provided w/o bus-host byte swapping.
247: */
248:
249: static __inline void
250: bus_space_read_raw_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
251: bus_size_t offset, u_int8_t *addr, size_t count)
252: {
253: volatile u_int16_t *s = __BA(tag, bsh, offset);
254: u_int16_t *laddr = (void *)addr;
255:
256: count = count >> 1;
257:
258: while (count--)
259: *laddr++ = *s++;
260: __asm __volatile("eieio; sync");
261: }
262:
263: static __inline void
264: bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
265: bus_size_t offset, u_int8_t *addr, size_t count)
266: {
267: volatile u_int32_t *s = __BA(tag, bsh, offset);
268: u_int32_t *laddr = (void *)addr;
269:
270: count = count >> 2;
271:
272: while (count--)
273: *laddr++ = *s++;
274: __asm __volatile("eieio; sync");
275: }
276:
277: #if 0 /* Cause a link error for bus_space_read_raw_region_8 */
278: #define bus_space_read_raw_region_8 \
279: !!! bus_space_read_raw_region_8 unimplemented !!!
280: #endif
281:
282:
283: /*
284: * void bus_space_write_raw_region_N(bus_space_tag_t tag,
285: * bus_space_handle_t bsh, bus_size_t offset,
286: * const u_intN_t *addr, size_t count);
287: *
288: * Write `count' bytes from the buffer provided to bus space described
289: * by tag/handle starting at `offset' w/o host-bus byte swapping.
290: */
291:
292: static __inline void
293: bus_space_write_raw_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
294: bus_size_t offset, const u_int8_t *addr, size_t count)
295: {
296: volatile u_int16_t *d = __BA(tag, bsh, offset);
297: const u_int16_t *laddr = (void *)addr;
298:
299: count = count >> 1;
300:
301: while (count--)
302: *d++ = *laddr++;
303: __asm __volatile("eieio; sync");
304: }
305:
306: static __inline void
307: bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
308: bus_size_t offset, const u_int8_t *addr, size_t count)
309: {
310: volatile u_int32_t *d = __BA(tag, bsh, offset);
311: const u_int32_t *laddr = (void *)addr;
312:
313: count = count >> 2;
314:
315: while (count--)
316: *d++ = *laddr++;
317: __asm __volatile("eieio; sync");
318: }
319:
320: #if 0
321: #define bus_space_write_raw_region_8 \
322: !!! bus_space_write_raw_region_8 unimplemented !!!
323: #endif
324:
325: /*
326: * void bus_space_set_multi_N(bus_space_tag_t tag,
327: * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
328: * size_t count);
329: *
330: * Write the 1, 2, 4, or 8 byte value `val' to bus space described
331: * by tag/handle/offset `count' times.
332: */
333: static __inline void bus_space_set_multi_1(bus_space_tag_t,
334: bus_space_handle_t, bus_size_t, u_int8_t, size_t);
335: static __inline void bus_space_set_multi_2(bus_space_tag_t,
336: bus_space_handle_t, bus_size_t, u_int16_t, size_t);
337: static __inline void bus_space_set_multi_4(bus_space_tag_t,
338: bus_space_handle_t, bus_size_t, u_int32_t, size_t);
339:
340: static __inline void
341: bus_space_set_multi_1(tag, bsh, offset, val, count)
342: bus_space_tag_t tag;
343: bus_space_handle_t bsh;
344: bus_size_t offset;
345: u_int8_t val;
346: size_t count;
347: {
348: volatile u_int8_t *d = __BA(tag, bsh, offset);
349:
350: while (count--)
351: *d = val;
352: __asm__ volatile("eieio; sync");
353: }
354:
355: static __inline void
356: bus_space_set_multi_2(tag, bsh, offset, val, count)
357: bus_space_tag_t tag;
358: bus_space_handle_t bsh;
359: bus_size_t offset;
360: u_int16_t val;
361: size_t count;
362: {
363: volatile u_int16_t *d = __BA(tag, bsh, offset);
364:
365: while (count--)
366: __asm__ volatile("sthbrx %0, 0, %1" ::
367: "r"(val), "r"(d));
368: __asm__ volatile("eieio; sync");
369: }
370:
371: static __inline void
372: bus_space_set_multi_4(tag, bsh, offset, val, count)
373: bus_space_tag_t tag;
374: bus_space_handle_t bsh;
375: bus_size_t offset;
376: u_int32_t val;
377: size_t count;
378: {
379: volatile u_int32_t *d = __BA(tag, bsh, offset);
380:
381: while (count--)
382: __asm__ volatile("stwbrx %0, 0, %1" ::
383: "r"(val), "r"(d));
384: __asm__ volatile("eieio; sync");
385: }
386:
387: #define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!!
388:
389: /* These are OpenBSD extensions to the general NetBSD bus interface. */
390: void
391: bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
392: bus_addr_t ba, u_int8_t *dst, bus_size_t size);
393: void
394: bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
395: bus_addr_t ba, u_int8_t *dst, bus_size_t size);
396: #define bus_space_read_raw_multi_8 \
397: !!! bus_space_read_raw_multi_8 not implemented !!!
398:
399: void
400: bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
401: bus_addr_t ba, const u_int8_t *src, bus_size_t size);
402: void
403: bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
404: bus_addr_t ba, const u_int8_t *src, bus_size_t size);
405: #define bus_space_write_raw_multi_8 \
406: !!! bus_space_write_raw_multi_8 not implemented !!!
407:
408: void
409: bus_space_set_region_1(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
410: u_int8_t val, bus_size_t c);
411: void
412: bus_space_set_region_2(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
413: u_int16_t val, bus_size_t c);
414: void
415: bus_space_set_region_4(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
416: u_int32_t val, bus_size_t c);
417: #define bus_space_set_region_8 \
418: !!! bus_space_set_region_8 not implemented !!!
419:
420: void
421: bus_space_copy_1(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
422: bus_size_t o1, bus_size_t o2, bus_size_t c);
423: void
424: bus_space_copy_2(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
425: bus_size_t o1, bus_size_t o2, bus_size_t c);
426: void
427: bus_space_copy_4(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
428: bus_size_t o1, bus_size_t o2, bus_size_t c);
429: #define bus_space_copy_8 \
430: !!! bus_space_write_raw_multi_8 not implemented !!!
431:
432: /*
433: * Bus read/write barrier methods.
434: *
435: * void bus_space_barrier(bus_space_tag_t tag,
436: * bus_space_handle_t bsh, bus_size_t offset,
437: * bus_size_t len, int flags);
438: *
439: * Note: powerpc does not currently implement barriers, but we must
440: * provide the flags to MI code.
441: * the processor does have eieio which is effectively the barrier
442: * operator, however due to how memory is mapped this should? not
443: * be required.
444: */
445: #define bus_space_barrier(t, h, o, l, f) \
446: ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
447: #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
448: #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
449: /* Compatibility defines */
450: #define BUS_BARRIER_READ BUS_SPACE_BARRIER_READ
451: #define BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE
452:
453:
454: #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
455: #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
456: #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
457: #define BUS_DMAMEM_NOSYNC 0x004
458: #define BUS_DMA_COHERENT 0x008 /* hint: map memory DMA coherent */
459: #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
460: #define BUS_DMA_BUS2 0x020
461: #define BUS_DMA_BUS3 0x040
462: #define BUS_DMA_BUS4 0x080
463: #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
464: #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
465: #define BUS_DMA_STREAMING 0x400 /* hint: sequential, unidirectional */
466:
467:
468: /* Forwards needed by prototypes below. */
469: struct mbuf;
470: struct proc;
471: struct uio;
472:
473: #define BUS_DMASYNC_POSTREAD 0x01
474: #define BUS_DMASYNC_POSTWRITE 0x02
475: #define BUS_DMASYNC_PREREAD 0x04
476: #define BUS_DMASYNC_PREWRITE 0x08
477:
478: typedef struct powerpc_bus_dma_tag *bus_dma_tag_t;
479: typedef struct powerpc_bus_dmamap *bus_dmamap_t;
480:
481: /*
482: * bus_dma_segment_t
483: *
484: * Describes a single contiguous DMA transaction. Values
485: * are suitable for programming into DMA registers.
486: */
487: struct powerpc_bus_dma_segment {
488: bus_addr_t ds_addr; /* DMA address */
489: bus_size_t ds_len; /* length of transfer */
490: };
491: typedef struct powerpc_bus_dma_segment bus_dma_segment_t;
492:
493: /*
494: * bus_dma_tag_t
495: *
496: * A machine-dependent opaque type describing the implementation of
497: * DMA for a given bus.
498: */
499:
500: struct powerpc_bus_dma_tag {
501: void *_cookie; /* cookie used in the guts */
502:
503: /*
504: * DMA mapping methods.
505: */
506: int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
507: bus_size_t, bus_size_t, int, bus_dmamap_t *);
508: void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
509: int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
510: bus_size_t, struct proc *, int);
511: int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
512: struct mbuf *, int);
513: int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
514: struct uio *, int);
515: int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
516: bus_dma_segment_t *, int, bus_size_t, int);
517: void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
518: void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
519: bus_addr_t, bus_size_t, int);
520:
521: /*
522: * DMA memory utility functions.
523: */
524: int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
525: bus_size_t, bus_dma_segment_t *, int, int *, int);
526: void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
527: int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
528: int, size_t, caddr_t *, int);
529: void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
530: paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
531: int, off_t, int, int);
532: };
533:
534: #define bus_dmamap_create(t, s, n, m, b, f, p) \
535: (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
536: #define bus_dmamap_destroy(t, p) \
537: (*(t)->_dmamap_destroy)((t), (p))
538: #define bus_dmamap_load(t, m, b, s, p, f) \
539: (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
540: #define bus_dmamap_load_mbuf(t, m, b, f) \
541: (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
542: #define bus_dmamap_load_uio(t, m, u, f) \
543: (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
544: #define bus_dmamap_load_raw(t, m, sg, n, s, f) \
545: (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
546: #define bus_dmamap_unload(t, p) \
547: (*(t)->_dmamap_unload)((t), (p))
548: #define bus_dmamap_sync(t, p, a, l, o) \
549: (void)((t)->_dmamap_sync ? \
550: (*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
551:
552: #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
553: (*(t)->_dmamem_alloc)((t)->_cookie, (s), (a), (b), (sg), (n), (r), (f))
554: #define bus_dmamem_free(t, sg, n) \
555: (*(t)->_dmamem_free)((t)->_cookie, (sg), (n))
556: #define bus_dmamem_map(t, sg, n, s, k, f) \
557: (*(t)->_dmamem_map)((t)->_cookie, (sg), (n), (s), (k), (f))
558: #define bus_dmamem_unmap(t, k, s) \
559: (*(t)->_dmamem_unmap)((t)->_cookie, (k), (s))
560: #define bus_dmamem_mmap(t, sg, n, o, p, f) \
561: (*(t)->_dmamem_mmap)((t)->_cookie, (sg), (n), (o), (p), (f))
562:
563: int _dmamap_create(bus_dma_tag_t, bus_size_t, int,
564: bus_size_t, bus_size_t, int, bus_dmamap_t *);
565: void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
566: int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
567: bus_size_t, struct proc *, int);
568: int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
569: int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
570: int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
571: bus_dma_segment_t *, int, bus_size_t, int);
572: void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
573: void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, bus_size_t,
574: int);
575:
576: int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
577: bus_size_t, bus_dma_segment_t *, int, int *, int);
578: void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
579: int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
580: int, size_t, caddr_t *, int);
581: void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
582: paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
583:
584: /*
585: * bus_dmamap_t
586: *
587: * Describes a DMA mapping.
588: */
589: struct powerpc_bus_dmamap {
590: /*
591: * PRIVATE MEMBERS: not for use by machine-independent code.
592: */
593: bus_size_t _dm_size; /* largest DMA transfer mappable */
594: int _dm_segcnt; /* number of segs this map can map */
595: bus_size_t _dm_maxsegsz; /* largest possible segment */
596: bus_size_t _dm_boundary; /* don't cross this */
597: int _dm_flags; /* misc. flags */
598:
599: void *_dm_cookie; /* cookie for bus-specific functions */
600:
601: /*
602: * PUBLIC MEMBERS: these are used by machine-independent code.
603: */
604: bus_size_t dm_mapsize; /* size of the mapping */
605: int dm_nsegs; /* # valid segments in mapping */
606: bus_dma_segment_t dm_segs[1]; /* segments; variable length */
607: };
608:
609: #endif /* _MACHINE_BUS_H_ */
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