Annotation of sys/arch/macppc/dev/if_mc.c, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: if_mc.c,v 1.10 2007/04/22 22:31:14 deraadt Exp $ */
! 2: /* $NetBSD: if_mc.c,v 1.9.16.1 2006/06/21 14:53:13 yamt Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1997 David Huang <khym@bga.com>
! 6: * All rights reserved.
! 7: *
! 8: * Portions of this code are based on code by Denton Gentry <denny1@home.com>
! 9: * and Yanagisawa Takeshi <yanagisw@aa.ap.titech.ac.jp>.
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. The name of the author may not be used to endorse or promote products
! 17: * derived from this software without specific prior written permission
! 18: *
! 19: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 20: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 21: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 22: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 23: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 24: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 25: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 26: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 27: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 28: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 29: *
! 30: */
! 31:
! 32: /*
! 33: * AMD AM79C940 (MACE) driver with DBDMA bus attachment and DMA routines
! 34: * for onboard ethernet found on most old world macs.
! 35: */
! 36:
! 37: #include <sys/param.h>
! 38: #include <sys/systm.h>
! 39: #include <sys/mbuf.h>
! 40: #include <sys/buf.h>
! 41: #include <sys/protosw.h>
! 42: #include <sys/socket.h>
! 43: #include <sys/syslog.h>
! 44: #include <sys/ioctl.h>
! 45: #include <sys/errno.h>
! 46: #include <sys/device.h>
! 47:
! 48: #include <net/if.h>
! 49: #include <net/if_dl.h>
! 50: #include <net/if_media.h>
! 51:
! 52: #include <uvm/uvm_extern.h>
! 53:
! 54: #ifdef INET
! 55: #include <netinet/in.h>
! 56: #include <netinet/if_ether.h>
! 57: #include <netinet/in_systm.h>
! 58: #include <netinet/in_var.h>
! 59: #include <netinet/ip.h>
! 60: #endif
! 61:
! 62: #include "bpfilter.h"
! 63: #if NBPFILTER > 0
! 64: #include <net/bpf.h>
! 65: #include <net/bpfdesc.h>
! 66: #endif
! 67:
! 68: #include <dev/ofw/openfirm.h>
! 69: #include <machine/pio.h>
! 70: #include <machine/bus.h>
! 71: #include <machine/autoconf.h>
! 72:
! 73: #include <macppc/dev/dbdma.h>
! 74:
! 75: #define MC_REGSPACING 16
! 76: #define MC_REGSIZE MACE_NREGS * MC_REGSPACING
! 77: #define MACE_REG(x) ((x)*MC_REGSPACING)
! 78: #define MACE_BUFLEN 2048
! 79: #define MACE_TXBUFS 2
! 80: #define MACE_RXBUFS 8
! 81:
! 82: #define MC_RXDMABUFS 4
! 83:
! 84: #define MACE_BUFSZ ((MACE_RXBUFS + MACE_TXBUFS + 2) * MACE_BUFLEN)
! 85:
! 86: #define NIC_GET(sc, reg) (in8rb(sc->sc_reg + MACE_REG(reg)))
! 87:
! 88: #define NIC_PUT(sc, reg, val) (out8rb(sc->sc_reg + MACE_REG(reg), (val)))
! 89:
! 90: /*
! 91: * AMD MACE (Am79C940) register definitions
! 92: */
! 93: #define MACE_RCVFIFO 0 /* Receive FIFO [15-00] (read only) */
! 94: #define MACE_XMTFIFO 1 /* Transmit FIFO [15-00] (write only) */
! 95: #define MACE_XMTFC 2 /* Transmit Frame Control (read/write) */
! 96: #define MACE_XMTFS 3 /* Transmit Frame Status (read only) */
! 97: #define MACE_XMTRC 4 /* Transmit Retry Count (read only) */
! 98: #define MACE_RCVFC 5 /* Receive Frame Control (read/write) */
! 99: #define MACE_RCVFS 6 /* Receive Frame Status (4 bytes) (read only) */
! 100: #define MACE_FIFOFC 7 /* FIFO Frame Count (read only) */
! 101: #define MACE_IR 8 /* Interrupt Register (read only) */
! 102: #define MACE_IMR 9 /* Interrupt Mask Register (read/write) */
! 103: #define MACE_PR 10 /* Poll Register (read only) */
! 104: #define MACE_BIUCC 11 /* BIU Configuration Control (read/write) */
! 105: #define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */
! 106: #define MACE_MACCC 13 /* MAC Configuration Control (read/write) */
! 107: #define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */
! 108: #define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */
! 109: #define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */
! 110: #define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */
! 111: #define MACE_IAC 18 /* Internal Address Configuration (read/write) */
! 112: /* RESERVED 19 Reserved (read/write as 0) */
! 113: #define MACE_LADRF 20 /* Logical Address Filter (8 bytes) (read/write) */
! 114: #define MACE_PADR 21 /* Physical Address (6 bytes) (read/write) */
! 115: /* RESERVED 22 Reserved (read/write as 0) */
! 116: /* RESERVED 23 Reserved (read/write as 0) */
! 117: #define MACE_MPC 24 /* Missed Packet Count (read only) */
! 118: /* RESERVED 25 Reserved (read/write as 0) */
! 119: #define MACE_RNTPC 26 /* Runt Packet Count (read only) */
! 120: #define MACE_RCVCC 27 /* Receive Collision Count (read only) */
! 121: /* RESERVED 28 Reserved (read/write as 0) */
! 122: #define MACE_UTR 29 /* User Test Register (read/write) */
! 123: #define MACE_RTR1 30 /* Reserved Test Register 1 (read/write as 0) */
! 124: #define MACE_RTR2 31 /* Reserved Test Register 2 (read/write as 0) */
! 125:
! 126: #define MACE_NREGS 32
! 127:
! 128: /* 2: Transmit Frame Control (XMTFC) */
! 129: #define DRTRY 0x80 /* Disable Retry */
! 130: #define DXMTFCS 0x08 /* Disable Transmit FCS */
! 131: #define APADXMT 0x01 /* Auto Pad Transmit */
! 132:
! 133: /* 3: Transmit Frame Status (XMTFS) */
! 134: #define XMTSV 0x80 /* Transmit Status Valid */
! 135: #define UFLO 0x40 /* Underflow */
! 136: #define LCOL 0x20 /* Late Collision */
! 137: #define MORE 0x10 /* More than one retry needed */
! 138: #define ONE 0x08 /* Exactly one retry needed */
! 139: #define DEFER 0x04 /* Transmission deferred */
! 140: #define LCAR 0x02 /* Loss of Carrier */
! 141: #define RTRY 0x01 /* Retry Error */
! 142:
! 143: /* 4: Transmit Retry Count (XMTRC) */
! 144: #define EXDEF 0x80 /* Excessive Defer */
! 145: #define XMTRC 0x0f /* Transmit Retry Count */
! 146:
! 147: /* 5: Receive Frame Control (RCVFC) */
! 148: #define LLRCV 0x08 /* Low Latency Receive */
! 149: #define MR 0x04 /* Match/Reject */
! 150: #define ASTRPRCV 0x01 /* Auto Strip Receive */
! 151:
! 152: /* 6: Receive Frame Status (RCVFS) */
! 153: /* 4 byte register; read 4 times to get all of the bytes */
! 154: /* Read 1: RFS0 - Receive Message Byte Count [7-0] (RCVCNT) */
! 155:
! 156: /* Read 2: RFS1 - Receive Status (RCVSTS) */
! 157: #define OFLO 0x80 /* Overflow flag */
! 158: #define CLSN 0x40 /* Collision flag */
! 159: #define FRAM 0x20 /* Framing Error flag */
! 160: #define FCS 0x10 /* FCS Error flag */
! 161: #define RCVCNT 0x0f /* Receive Message Byte Count [11-8] */
! 162:
! 163: /* Read 3: RFS2 - Runt Packet Count (RNTPC) [7-0] */
! 164:
! 165: /* Read 4: RFS3 - Receive Collision Count (RCVCC) [7-0] */
! 166:
! 167: /* 7: FIFO Frame Count (FIFOFC) */
! 168: #define RCVFC 0xf0 /* Receive Frame Count */
! 169: #define XMTFC 0x0f /* Transmit Frame Count */
! 170:
! 171: /* 8: Interrupt Register (IR) */
! 172: #define JAB 0x80 /* Jabber Error */
! 173: #define BABL 0x40 /* Babble Error */
! 174: #define CERR 0x20 /* Collision Error */
! 175: #define RCVCCO 0x10 /* Receive Collision Count Overflow */
! 176: #define RNTPCO 0x08 /* Runt Packet Count Overflow */
! 177: #define MPCO 0x04 /* Missed Packet Count Overflow */
! 178: #define RCVINT 0x02 /* Receive Interrupt */
! 179: #define XMTINT 0x01 /* Transmit Interrupt */
! 180:
! 181: /* 9: Interrut Mask Register (IMR) */
! 182: #define JABM 0x80 /* Jabber Error Mask */
! 183: #define BABLM 0x40 /* Babble Error Mask */
! 184: #define CERRM 0x20 /* Collision Error Mask */
! 185: #define RCVCCOM 0x10 /* Receive Collision Count Overflow Mask */
! 186: #define RNTPCOM 0x08 /* Runt Packet Count Overflow Mask */
! 187: #define MPCOM 0x04 /* Missed Packet Count Overflow Mask */
! 188: #define RCVINTM 0x02 /* Receive Interrupt Mask */
! 189: #define XMTINTM 0x01 /* Transmit Interrupt Mask */
! 190:
! 191: /* 10: Poll Register (PR) */
! 192: #define XMTSV 0x80 /* Transmit Status Valid */
! 193: #define TDTREQ 0x40 /* Transmit Data Transfer Request */
! 194: #define RDTREQ 0x20 /* Receive Data Transfer Request */
! 195:
! 196: /* 11: BIU Configuration Control (BIUCC) */
! 197: #define BSWP 0x40 /* Byte Swap */
! 198: #define XMTSP 0x30 /* Transmit Start Point */
! 199: #define XMTSP_4 0x00 /* 4 bytes */
! 200: #define XMTSP_16 0x10 /* 16 bytes */
! 201: #define XMTSP_64 0x20 /* 64 bytes */
! 202: #define XMTSP_112 0x30 /* 112 bytes */
! 203: #define SWRST 0x01 /* Software Reset */
! 204:
! 205: /* 12: FIFO Configuration Control (FIFOCC) */
! 206: #define XMTFW 0xc0 /* Transmit FIFO Watermark */
! 207: #define XMTFW_8 0x00 /* 8 write cycles */
! 208: #define XMTFW_16 0x40 /* 16 write cycles */
! 209: #define XMTFW_32 0x80 /* 32 write cycles */
! 210: #define RCVFW 0x30 /* Receive FIFO Watermark */
! 211: #define RCVFW_16 0x00 /* 16 bytes */
! 212: #define RCVFW_32 0x10 /* 32 bytes */
! 213: #define RCVFW_64 0x20 /* 64 bytes */
! 214: #define XMTFWU 0x08 /* Transmit FIFO Watermark Update */
! 215: #define RCVFWU 0x04 /* Receive FIFO Watermark Update */
! 216: #define XMTBRST 0x02 /* Transmit Burst */
! 217: #define RCVBRST 0x01 /* Receive Burst */
! 218:
! 219: /* 13: MAC Configuration (MACCC) */
! 220: #define PROM 0x80 /* Promiscuous */
! 221: #define DXMT2PD 0x40 /* Disable Transmit Two Part Deferral */
! 222: #define EMBA 0x20 /* Enable Modified Back-off Algorithm */
! 223: #define DRCVPA 0x08 /* Disable Receive Physical Address */
! 224: #define DRCVBC 0x04 /* Disable Receive Broadcast */
! 225: #define ENXMT 0x02 /* Enable Transmit */
! 226: #define ENRCV 0x01 /* Enable Receive */
! 227:
! 228: /* 14: PLS Configuration Control (PLSCC) */
! 229: #define XMTSEL 0x08 /* Transmit Mode Select */
! 230: #define PORTSEL 0x06 /* Port Select */
! 231: #define PORTSEL_AUI 0x00 /* Select AUI */
! 232: #define PORTSEL_10BT 0x02 /* Select 10BASE-T */
! 233: #define PORTSEL_DAI 0x04 /* Select DAI port */
! 234: #define PORTSEL_GPSI 0x06 /* Select GPSI */
! 235: #define ENPLSIO 0x01 /* Enable PLS I/O */
! 236:
! 237: /* 15: PHY Configuration (PHYCC) */
! 238: #define LNKFL 0x80 /* Link Fail */
! 239: #define DLNKTST 0x40 /* Disable Link Test */
! 240: #define REVPOL 0x20 /* Reversed Polarity */
! 241: #define DAPC 0x10 /* Disable Auto Polarity Correction */
! 242: #define LRT 0x08 /* Low Receive Threshold */
! 243: #define ASEL 0x04 /* Auto Select */
! 244: #define RWAKE 0x02 /* Remote Wake */
! 245: #define AWAKE 0x01 /* Auto Wake */
! 246:
! 247: /* 18: Internal Address Configuration (IAC) */
! 248: #define ADDRCHG 0x80 /* Address Change */
! 249: #define PHYADDR 0x04 /* Physical Address Reset */
! 250: #define LOGADDR 0x02 /* Logical Address Reset */
! 251:
! 252: /* 28: User Test Register (UTR) */
! 253: #define RTRE 0x80 /* Reserved Test Register Enable */
! 254: #define RTRD 0x40 /* Reserved Test Register Disable */
! 255: #define RPA 0x20 /* Run Packet Accept */
! 256: #define FCOLL 0x10 /* Force Collision */
! 257: #define RCVFCSE 0x08 /* Receive FCS Enable */
! 258: #define LOOP 0x06 /* Loopback Control */
! 259: #define LOOP_NONE 0x00 /* No Loopback */
! 260: #define LOOP_EXT 0x02 /* External Loopback */
! 261: #define LOOP_INT 0x04 /* Internal Loopback, excludes MENDEC */
! 262: #define LOOP_INT_MENDEC 0x06 /* Internal Loopback, includes MENDEC */
! 263:
! 264: struct mc_rxframe {
! 265: u_int8_t rx_rcvcnt;
! 266: u_int8_t rx_rcvsts;
! 267: u_int8_t rx_rntpc;
! 268: u_int8_t rx_rcvcc;
! 269: u_char *rx_frame;
! 270: };
! 271:
! 272: struct mc_softc {
! 273: struct device sc_dev; /* base device glue */
! 274: struct arpcom sc_arpcom; /* Ethernet common part */
! 275: struct timeout sc_tick_ch;
! 276:
! 277: struct mc_rxframe sc_rxframe;
! 278: u_int8_t sc_biucc;
! 279: u_int8_t sc_fifocc;
! 280: u_int8_t sc_plscc;
! 281: u_int8_t sc_enaddr[6];
! 282: u_int8_t sc_pad[2];
! 283: int sc_havecarrier; /* carrier status */
! 284:
! 285: char *sc_reg;
! 286: bus_dma_tag_t sc_dmat;
! 287: bus_dmamap_t sc_bufmap;
! 288: bus_dma_segment_t sc_bufseg[1];
! 289:
! 290: dbdma_regmap_t *sc_txdma;
! 291: dbdma_regmap_t *sc_rxdma;
! 292: dbdma_command_t *sc_txdmacmd;
! 293: dbdma_command_t *sc_rxdmacmd;
! 294: dbdma_t sc_txdbdma;
! 295: dbdma_t sc_rxdbdma;
! 296:
! 297: caddr_t sc_txbuf;
! 298: caddr_t sc_rxbuf;
! 299: paddr_t sc_txbuf_pa;
! 300: paddr_t sc_rxbuf_pa;
! 301: int sc_tail;
! 302: int sc_rxset;
! 303: int sc_txset;
! 304: int sc_txseti;
! 305: };
! 306:
! 307: int mc_match(struct device *, void *, void *);
! 308: void mc_attach(struct device *, struct device *, void *);
! 309:
! 310: struct cfattach mc_ca = {
! 311: sizeof(struct mc_softc), mc_match, mc_attach
! 312: };
! 313:
! 314: struct cfdriver mc_cd = {
! 315: NULL, "mc", DV_IFNET
! 316: };
! 317:
! 318: void mc_init(struct mc_softc *sc);
! 319: void mc_put(struct mc_softc *sc, u_int len);
! 320: int mc_dmaintr(void *arg);
! 321: void mc_reset_rxdma(struct mc_softc *sc);
! 322: void mc_reset_txdma(struct mc_softc *sc);
! 323: int mc_stop(struct mc_softc *sc);
! 324: int mc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
! 325: void mc_start(struct ifnet *ifp);
! 326: void mc_reset(struct mc_softc *sc);
! 327: void mc_tint(struct mc_softc *sc);
! 328: void mc_rint(struct mc_softc *sc);
! 329: int mc_intr(void *);
! 330: void mc_watchdog(struct ifnet *ifp);
! 331:
! 332: u_int maceput(struct mc_softc *sc, struct mbuf *);
! 333: void mace_read(struct mc_softc *, caddr_t, int);
! 334: struct mbuf *mace_get(struct mc_softc *, caddr_t, int);
! 335: static void mace_calcladrf(struct mc_softc *, u_int8_t *);
! 336: void mc_putpacket(struct mc_softc *, u_int);
! 337:
! 338: int
! 339: mc_match(struct device *parent, void *arg, void *aux)
! 340: {
! 341: struct confargs *ca = aux;
! 342:
! 343: if (strcmp(ca->ca_name, "mace") != 0)
! 344: return 0;
! 345:
! 346: /* requires 6 regs */
! 347: if (ca->ca_nreg / sizeof(int) != 6)
! 348: return 0;
! 349:
! 350: /* requires 3 intrs */
! 351: if (ca->ca_nintr / sizeof(int) != 3)
! 352: return 0;
! 353:
! 354: return 1;
! 355: }
! 356:
! 357: void
! 358: mc_attach(struct device *parent, struct device *self, void *aux)
! 359: {
! 360: struct confargs *ca = aux;
! 361: struct mc_softc *sc = (struct mc_softc *)self;
! 362: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 363: u_int8_t lladdr[ETHER_ADDR_LEN];
! 364: int nseg, error;
! 365:
! 366: if (OF_getprop(ca->ca_node, "local-mac-address", lladdr,
! 367: ETHER_ADDR_LEN) != ETHER_ADDR_LEN) {
! 368: printf(": failed to get MAC address.\n");
! 369: return;
! 370: }
! 371:
! 372: ca->ca_reg[0] += ca->ca_baseaddr;
! 373: ca->ca_reg[2] += ca->ca_baseaddr;
! 374: ca->ca_reg[4] += ca->ca_baseaddr;
! 375:
! 376: if ((sc->sc_reg = mapiodev(ca->ca_reg[0], ca->ca_reg[1])) == NULL) {
! 377: printf(": cannot map registers\n");
! 378: return;
! 379: }
! 380:
! 381: sc->sc_dmat = ca->ca_dmat;
! 382: sc->sc_tail = 0;
! 383:
! 384: if ((sc->sc_txdma = mapiodev(ca->ca_reg[2], ca->ca_reg[3])) == NULL) {
! 385: printf(": cannot map TX DMA registers\n");
! 386: goto notxdma;
! 387: }
! 388: if ((sc->sc_rxdma = mapiodev(ca->ca_reg[4], ca->ca_reg[5])) == NULL) {
! 389: printf(": cannot map RX DMA registers\n");
! 390: goto norxdma;
! 391: }
! 392: if ((sc->sc_txdbdma = dbdma_alloc(sc->sc_dmat, 2)) == NULL) {
! 393: printf(": cannot alloc TX DMA descriptors\n");
! 394: goto notxdbdma;
! 395: }
! 396: sc->sc_txdmacmd = sc->sc_txdbdma->d_addr;
! 397:
! 398: if ((sc->sc_rxdbdma = dbdma_alloc(sc->sc_dmat, 8 + 1)) == NULL) {
! 399: printf(": cannot alloc RX DMA descriptors\n");
! 400: goto norxdbdma;
! 401: }
! 402: sc->sc_rxdmacmd = sc->sc_rxdbdma->d_addr;
! 403:
! 404: if ((error = bus_dmamem_alloc(sc->sc_dmat, MACE_BUFSZ, PAGE_SIZE, 0,
! 405: sc->sc_bufseg, 1, &nseg, BUS_DMA_NOWAIT))) {
! 406: printf(": cannot allocate DMA mem (%d)\n", error);
! 407: goto nodmamem;
! 408: }
! 409:
! 410: if ((error = bus_dmamem_map(sc->sc_dmat, sc->sc_bufseg, nseg,
! 411: MACE_BUFSZ, &sc->sc_txbuf, BUS_DMA_NOWAIT))) {
! 412: printf(": cannot map DMA mem (%d)\n", error);
! 413: goto nodmamap;
! 414: }
! 415:
! 416: if ((error = bus_dmamap_create(sc->sc_dmat, MACE_BUFSZ, 1, MACE_BUFSZ,
! 417: 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_bufmap))) {
! 418: printf(": cannot create DMA map (%d)\n", error);
! 419: goto nodmacreate;
! 420: }
! 421:
! 422: if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_bufmap, sc->sc_txbuf,
! 423: MACE_BUFSZ, NULL, BUS_DMA_NOWAIT))) {
! 424: printf(": cannot load DMA map (%d)\n", error);
! 425: goto nodmaload;
! 426: }
! 427:
! 428: sc->sc_txbuf_pa = sc->sc_bufmap->dm_segs->ds_addr;
! 429: sc->sc_rxbuf = sc->sc_txbuf + MACE_BUFLEN * MACE_TXBUFS;
! 430: sc->sc_rxbuf_pa = sc->sc_txbuf_pa + MACE_BUFLEN * MACE_TXBUFS;
! 431:
! 432: printf(": irq %d,%d,%d", ca->ca_intr[0], ca->ca_intr[1],
! 433: ca->ca_intr[2]);
! 434:
! 435: /* disable receive DMA */
! 436: dbdma_reset(sc->sc_rxdma);
! 437:
! 438: /* disable transmit DMA */
! 439: dbdma_reset(sc->sc_txdma);
! 440:
! 441: /* install interrupt handlers */
! 442: mac_intr_establish(parent, ca->ca_intr[2], IST_LEVEL, IPL_NET,
! 443: mc_dmaintr, sc, sc->sc_dev.dv_xname);
! 444: mac_intr_establish(parent, ca->ca_intr[0], IST_LEVEL, IPL_NET,
! 445: mc_intr, sc, sc->sc_dev.dv_xname);
! 446:
! 447: sc->sc_biucc = XMTSP_64;
! 448: sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU |
! 449: XMTBRST | RCVBRST;
! 450: sc->sc_plscc = PORTSEL_GPSI | ENPLSIO;
! 451:
! 452: /* reset the chip and disable all interrupts */
! 453: NIC_PUT(sc, MACE_BIUCC, SWRST);
! 454: DELAY(100);
! 455:
! 456: NIC_PUT(sc, MACE_IMR, ~0);
! 457:
! 458: bcopy(lladdr, sc->sc_enaddr, ETHER_ADDR_LEN);
! 459: bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
! 460: printf(": address %s\n", ether_sprintf(lladdr));
! 461:
! 462: bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
! 463: ifp->if_softc = sc;
! 464: ifp->if_ioctl = mc_ioctl;
! 465: ifp->if_start = mc_start;
! 466: ifp->if_flags =
! 467: IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
! 468: ifp->if_watchdog = mc_watchdog;
! 469: ifp->if_timer = 0;
! 470: IFQ_SET_READY(&ifp->if_snd);
! 471:
! 472: if_attach(ifp);
! 473: ether_ifattach(ifp);
! 474:
! 475: return;
! 476: nodmaload:
! 477: bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufmap);
! 478: nodmacreate:
! 479: bus_dmamem_unmap(sc->sc_dmat, sc->sc_txbuf, MACE_BUFSZ);
! 480: nodmamap:
! 481: bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, 1);
! 482: nodmamem:
! 483: dbdma_free(sc->sc_rxdbdma);
! 484: norxdbdma:
! 485: dbdma_free(sc->sc_txdbdma);
! 486: notxdbdma:
! 487: unmapiodev((void *)sc->sc_rxdma, ca->ca_reg[5]);
! 488: norxdma:
! 489: unmapiodev((void *)sc->sc_txdma, ca->ca_reg[3]);
! 490: notxdma:
! 491: unmapiodev(sc->sc_reg, ca->ca_reg[1]);
! 492: }
! 493:
! 494: int
! 495: mc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
! 496: {
! 497: struct mc_softc *sc = ifp->if_softc;
! 498: struct ifaddr *ifa = (struct ifaddr *)data;
! 499: struct ifreq *ifr;
! 500:
! 501: int s = splnet(), err = 0;
! 502:
! 503: switch (cmd) {
! 504:
! 505: case SIOCSIFADDR:
! 506: ifp->if_flags |= IFF_UP;
! 507: if (!(ifp->if_flags & IFF_RUNNING))
! 508: mc_init(sc);
! 509: #ifdef INET
! 510: if (ifa->ifa_addr->sa_family == AF_INET)
! 511: arp_ifinit(&sc->sc_arpcom, ifa);
! 512: #endif
! 513: break;
! 514:
! 515: case SIOCSIFFLAGS:
! 516: if ((ifp->if_flags & IFF_UP) == 0 &&
! 517: (ifp->if_flags & IFF_RUNNING) != 0) {
! 518: /*
! 519: * If interface is marked down and it is running,
! 520: * then stop it.
! 521: */
! 522: mc_stop(sc);
! 523: } else if ((ifp->if_flags & IFF_UP) != 0 &&
! 524: (ifp->if_flags & IFF_RUNNING) == 0) {
! 525: /*
! 526: * If interface is marked up and it is stopped,
! 527: * then start it.
! 528: */
! 529: mc_init(sc);
! 530: } else {
! 531: /*
! 532: * reset the interface to pick up any other changes
! 533: * in flags
! 534: */
! 535: mc_reset(sc);
! 536: mc_start(ifp);
! 537: }
! 538: break;
! 539:
! 540: case SIOCADDMULTI:
! 541: case SIOCDELMULTI:
! 542: ifr = (struct ifreq *) data;
! 543: err = (cmd == SIOCADDMULTI) ?
! 544: ether_addmulti(ifr, &sc->sc_arpcom) :
! 545: ether_delmulti(ifr, &sc->sc_arpcom);
! 546:
! 547: if (err == ENETRESET) {
! 548: /*
! 549: * Multicast list has changed; set the hardware
! 550: * filter accordingly. But remember UP flag!
! 551: */
! 552: if (ifp->if_flags & IFF_RUNNING)
! 553: mc_reset(sc);
! 554: err = 0;
! 555: }
! 556: break;
! 557: default:
! 558: err = EINVAL;
! 559: }
! 560: splx(s);
! 561: return (err);
! 562: }
! 563:
! 564: /*
! 565: * Encapsulate a packet of type family for the local net.
! 566: */
! 567: void
! 568: mc_start(struct ifnet *ifp)
! 569: {
! 570: struct mc_softc *sc = ifp->if_softc;
! 571: struct mbuf *m;
! 572:
! 573: if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
! 574: return;
! 575:
! 576: while (1) {
! 577: if (ifp->if_flags & IFF_OACTIVE)
! 578: return;
! 579:
! 580: IFQ_DEQUEUE(&ifp->if_snd, m);
! 581: if (m == NULL)
! 582: return;
! 583:
! 584: #if NBPFILTER > 0
! 585: /*
! 586: * If bpf is listening on this interface, let it
! 587: * see the packet before we commit it to the wire.
! 588: */
! 589: if (ifp->if_bpf)
! 590: bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
! 591: #endif
! 592:
! 593: /*
! 594: * Copy the mbuf chain into the transmit buffer.
! 595: */
! 596: ifp->if_flags |= IFF_OACTIVE;
! 597: maceput(sc, m);
! 598:
! 599: ifp->if_opackets++; /* # of pkts */
! 600: }
! 601: }
! 602:
! 603: /*
! 604: * reset and restart the MACE. Called in case of fatal
! 605: * hardware/software errors.
! 606: */
! 607: void
! 608: mc_reset(struct mc_softc *sc)
! 609: {
! 610: mc_stop(sc);
! 611: mc_init(sc);
! 612: }
! 613:
! 614: void
! 615: mc_init(struct mc_softc *sc)
! 616: {
! 617: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 618: u_int8_t maccc, ladrf[8];
! 619: int s, i;
! 620:
! 621: s = splnet();
! 622:
! 623: NIC_PUT(sc, MACE_BIUCC, sc->sc_biucc);
! 624: NIC_PUT(sc, MACE_FIFOCC, sc->sc_fifocc);
! 625: NIC_PUT(sc, MACE_IMR, ~0); /* disable all interrupts */
! 626: NIC_PUT(sc, MACE_PLSCC, sc->sc_plscc);
! 627:
! 628: NIC_PUT(sc, MACE_UTR, RTRD); /* disable reserved test registers */
! 629:
! 630: /* set MAC address */
! 631: NIC_PUT(sc, MACE_IAC, ADDRCHG);
! 632: while (NIC_GET(sc, MACE_IAC) & ADDRCHG)
! 633: ;
! 634: NIC_PUT(sc, MACE_IAC, PHYADDR);
! 635: for (i = 0; i < ETHER_ADDR_LEN; i++)
! 636: out8rb(sc->sc_reg + MACE_REG(MACE_PADR) + i,
! 637: sc->sc_enaddr[i]);
! 638:
! 639: /* set logical address filter */
! 640: mace_calcladrf(sc, ladrf);
! 641:
! 642: NIC_PUT(sc, MACE_IAC, ADDRCHG);
! 643: while (NIC_GET(sc, MACE_IAC) & ADDRCHG)
! 644: ;
! 645: NIC_PUT(sc, MACE_IAC, LOGADDR);
! 646: for (i = 0; i < 8; i++)
! 647: out8rb(sc->sc_reg + MACE_REG(MACE_LADRF) + i,
! 648: ladrf[i]);
! 649:
! 650: NIC_PUT(sc, MACE_XMTFC, APADXMT);
! 651: /*
! 652: * No need to autostrip padding on receive... Ethernet frames
! 653: * don't have a length field, unlike 802.3 frames, so the MACE
! 654: * can't figure out the length of the packet anyways.
! 655: */
! 656: NIC_PUT(sc, MACE_RCVFC, 0);
! 657:
! 658: maccc = ENXMT | ENRCV;
! 659: if (ifp->if_flags & IFF_PROMISC)
! 660: maccc |= PROM;
! 661:
! 662: NIC_PUT(sc, MACE_MACCC, maccc);
! 663:
! 664: mc_reset_rxdma(sc);
! 665: mc_reset_txdma(sc);
! 666: /*
! 667: * Enable all interrupts except receive, since we use the DMA
! 668: * completion interrupt for that.
! 669: */
! 670: NIC_PUT(sc, MACE_IMR, RCVINTM);
! 671:
! 672: /* flag interface as "running" */
! 673: ifp->if_flags |= IFF_RUNNING;
! 674: ifp->if_flags &= ~IFF_OACTIVE;
! 675:
! 676: splx(s);
! 677: }
! 678:
! 679: /*
! 680: * Close down an interface and free its buffers.
! 681: * Called on final close of device, or if mcinit() fails
! 682: * part way through.
! 683: */
! 684: int
! 685: mc_stop(struct mc_softc *sc)
! 686: {
! 687: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 688: int s;
! 689:
! 690: s = splnet();
! 691:
! 692: NIC_PUT(sc, MACE_BIUCC, SWRST);
! 693: DELAY(100);
! 694:
! 695: ifp->if_timer = 0;
! 696: ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
! 697:
! 698: splx(s);
! 699: return (0);
! 700: }
! 701:
! 702: /*
! 703: * Called if any Tx packets remain unsent after 5 seconds,
! 704: * In all cases we just reset the chip, and any retransmission
! 705: * will be handled by higher level protocol timeouts.
! 706: */
! 707: void
! 708: mc_watchdog(struct ifnet *ifp)
! 709: {
! 710: struct mc_softc *sc = ifp->if_softc;
! 711:
! 712: printf("mcwatchdog: resetting chip\n");
! 713: mc_reset(sc);
! 714: }
! 715:
! 716: int
! 717: mc_intr(void *arg)
! 718: {
! 719: struct mc_softc *sc = arg;
! 720: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 721: u_int8_t ir;
! 722:
! 723: ir = NIC_GET(sc, MACE_IR) & ~NIC_GET(sc, MACE_IMR);
! 724:
! 725: if (ir & JAB) {
! 726: #ifdef MCDEBUG
! 727: printf("%s: jabber error\n", sc->sc_dev.dv_xname);
! 728: #endif
! 729: ifp->if_oerrors++;
! 730: }
! 731:
! 732: if (ir & BABL) {
! 733: #ifdef MCDEBUG
! 734: printf("%s: babble\n", sc->sc_dev.dv_xname);
! 735: #endif
! 736: ifp->if_oerrors++;
! 737: }
! 738:
! 739: if (ir & CERR) {
! 740: #ifdef MCDEBUG
! 741: printf("%s: collision error\n", sc->sc_dev.dv_xname);
! 742: #endif
! 743: ifp->if_collisions++;
! 744: }
! 745:
! 746: /*
! 747: * Pretend we have carrier; if we don't this will be cleared
! 748: * shortly.
! 749: */
! 750: sc->sc_havecarrier = 1;
! 751:
! 752: if (ir & XMTINT)
! 753: mc_tint(sc);
! 754:
! 755: if (ir & RCVINT)
! 756: mc_rint(sc);
! 757:
! 758: return(1);
! 759: }
! 760:
! 761: void
! 762: mc_tint(struct mc_softc *sc)
! 763: {
! 764: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 765: u_int8_t xmtrc, xmtfs;
! 766:
! 767: xmtrc = NIC_GET(sc, MACE_XMTRC);
! 768: xmtfs = NIC_GET(sc, MACE_XMTFS);
! 769:
! 770: if ((xmtfs & XMTSV) == 0)
! 771: return;
! 772:
! 773: if (xmtfs & UFLO) {
! 774: printf("%s: underflow\n", sc->sc_dev.dv_xname);
! 775: mc_reset(sc);
! 776: return;
! 777: }
! 778:
! 779: if (xmtfs & LCOL) {
! 780: printf("%s: late collision\n", sc->sc_dev.dv_xname);
! 781: ifp->if_oerrors++;
! 782: ifp->if_collisions++;
! 783: }
! 784:
! 785: if (xmtfs & MORE)
! 786: /* Real number is unknown. */
! 787: ifp->if_collisions += 2;
! 788: else if (xmtfs & ONE)
! 789: ifp->if_collisions++;
! 790: else if (xmtfs & RTRY) {
! 791: printf("%s: excessive collisions\n", sc->sc_dev.dv_xname);
! 792: ifp->if_collisions += 16;
! 793: ifp->if_oerrors++;
! 794: }
! 795:
! 796: if (xmtfs & LCAR) {
! 797: sc->sc_havecarrier = 0;
! 798: printf("%s: lost carrier\n", sc->sc_dev.dv_xname);
! 799: ifp->if_oerrors++;
! 800: }
! 801:
! 802: ifp->if_flags &= ~IFF_OACTIVE;
! 803: ifp->if_timer = 0;
! 804: mc_start(ifp);
! 805: }
! 806:
! 807: void
! 808: mc_rint(struct mc_softc *sc)
! 809: {
! 810: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 811: #define rxf sc->sc_rxframe
! 812: u_int len;
! 813:
! 814: len = (rxf.rx_rcvcnt | ((rxf.rx_rcvsts & 0xf) << 8)) - 4;
! 815:
! 816: #ifdef MCDEBUG
! 817: if (rxf.rx_rcvsts & 0xf0)
! 818: printf("%s: rcvcnt %02x rcvsts %02x rntpc 0x%02x rcvcc 0x%02x\n",
! 819: sc->sc_dev.dv_xname, rxf.rx_rcvcnt, rxf.rx_rcvsts,
! 820: rxf.rx_rntpc, rxf.rx_rcvcc);
! 821: #endif
! 822:
! 823: if (rxf.rx_rcvsts & OFLO) {
! 824: #ifdef MCDEBUG
! 825: printf("%s: receive FIFO overflow\n", sc->sc_dev.dv_xname);
! 826: #endif
! 827: ifp->if_ierrors++;
! 828: return;
! 829: }
! 830:
! 831: if (rxf.rx_rcvsts & CLSN)
! 832: ifp->if_collisions++;
! 833:
! 834: if (rxf.rx_rcvsts & FRAM) {
! 835: #ifdef MCDEBUG
! 836: printf("%s: framing error\n", sc->sc_dev.dv_xname);
! 837: #endif
! 838: ifp->if_ierrors++;
! 839: return;
! 840: }
! 841:
! 842: if (rxf.rx_rcvsts & FCS) {
! 843: #ifdef MCDEBUG
! 844: printf("%s: frame control checksum error\n", sc->sc_dev.dv_xname);
! 845: #endif
! 846: ifp->if_ierrors++;
! 847: return;
! 848: }
! 849:
! 850: mace_read(sc, rxf.rx_frame, len);
! 851: #undef rxf
! 852: }
! 853: /*
! 854: * stuff packet into MACE (at splnet)
! 855: */
! 856: u_int
! 857: maceput(struct mc_softc *sc, struct mbuf *m)
! 858: {
! 859: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 860: struct mbuf *n;
! 861: u_int len, totlen = 0;
! 862: u_char *buff;
! 863:
! 864: buff = sc->sc_txbuf;
! 865:
! 866: for (; m; m = n) {
! 867: u_char *data = mtod(m, u_char *);
! 868: len = m->m_len;
! 869: totlen += len;
! 870: bcopy(data, buff, len);
! 871: buff += len;
! 872: MFREE(m, n);
! 873: }
! 874:
! 875: if (totlen > PAGE_SIZE)
! 876: panic("%s: maceput: packet overflow", sc->sc_dev.dv_xname);
! 877:
! 878: #if 0
! 879: if (totlen < ETHERMIN + sizeof(struct ether_header)) {
! 880: int pad = ETHERMIN + sizeof(struct ether_header) - totlen;
! 881: bzero(sc->sc_txbuf + totlen, pad);
! 882: totlen = ETHERMIN + sizeof(struct ether_header);
! 883: }
! 884: #endif
! 885:
! 886:
! 887: /* 5 seconds to watch for failing to transmit */
! 888: ifp->if_timer = 5;
! 889: mc_putpacket(sc, totlen);
! 890: return (totlen);
! 891: }
! 892:
! 893: void
! 894: mace_read(struct mc_softc *sc, caddr_t pkt, int len)
! 895: {
! 896: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 897: struct mbuf *m;
! 898:
! 899: if (len <= sizeof(struct ether_header) ||
! 900: len > ETHERMTU + sizeof(struct ether_header)) {
! 901: #ifdef MCDEBUG
! 902: printf("%s: invalid packet size %d; dropping\n",
! 903: sc->sc_dev.dv_xname, len);
! 904: #endif
! 905: ifp->if_ierrors++;
! 906: return;
! 907: }
! 908:
! 909: m = mace_get(sc, pkt, len);
! 910: if (m == NULL) {
! 911: ifp->if_ierrors++;
! 912: return;
! 913: }
! 914:
! 915: ifp->if_ipackets++;
! 916:
! 917: #if NBPFILTER > 0
! 918: /* Pass the packet to any BPF listeners. */
! 919: if (ifp->if_bpf)
! 920: bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
! 921: #endif
! 922:
! 923: /* Pass the packet up. */
! 924: ether_input_mbuf(ifp, m);
! 925: }
! 926:
! 927: /*
! 928: * Pull data off an interface.
! 929: * Len is length of data, with local net header stripped.
! 930: * We copy the data into mbufs. When full cluster sized units are present
! 931: * we copy into clusters.
! 932: */
! 933: struct mbuf *
! 934: mace_get(struct mc_softc *sc, caddr_t pkt, int totlen)
! 935: {
! 936: struct mbuf *m;
! 937: struct mbuf *top, **mp;
! 938: int len;
! 939:
! 940: MGETHDR(m, M_DONTWAIT, MT_DATA);
! 941: if (m == NULL)
! 942: return (NULL);
! 943:
! 944: m->m_pkthdr.rcvif = &sc->sc_arpcom.ac_if;
! 945: m->m_pkthdr.len = totlen;
! 946: len = MHLEN;
! 947: top = 0;
! 948: mp = ⊤
! 949:
! 950: while (totlen > 0) {
! 951: if (top) {
! 952: MGET(m, M_DONTWAIT, MT_DATA);
! 953: if (m == NULL) {
! 954: m_freem(top);
! 955: return (NULL);
! 956: }
! 957: len = MLEN;
! 958: }
! 959: if (totlen >= MINCLSIZE) {
! 960: MCLGET(m, M_DONTWAIT);
! 961: if ((m->m_flags & M_EXT) == 0) {
! 962: m_free(m);
! 963: m_freem(top);
! 964: return (NULL);
! 965: }
! 966: len = MCLBYTES;
! 967: }
! 968: m->m_len = len = min(totlen, len);
! 969: bcopy(pkt, mtod(m, caddr_t), len);
! 970: pkt += len;
! 971: totlen -= len;
! 972: *mp = m;
! 973: mp = &m->m_next;
! 974: }
! 975:
! 976: return (top);
! 977: }
! 978:
! 979: void
! 980: mc_putpacket(struct mc_softc *sc, u_int len)
! 981: {
! 982: dbdma_command_t *cmd = sc->sc_txdmacmd;
! 983:
! 984: DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_pa,
! 985: DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
! 986: cmd++;
! 987: DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, DBDMA_INT_ALWAYS,
! 988: DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
! 989:
! 990: dbdma_start(sc->sc_txdma, sc->sc_txdbdma);
! 991: }
! 992:
! 993: /*
! 994: * Interrupt handler for the MACE DMA completion interrupts
! 995: */
! 996: int
! 997: mc_dmaintr(void *arg)
! 998: {
! 999: struct mc_softc *sc = arg;
! 1000: int status, offset, statoff;
! 1001: int datalen, resid;
! 1002: int i, n, count;
! 1003: dbdma_command_t *cmd;
! 1004:
! 1005: /* We've received some packets from the MACE */
! 1006: /* Loop through, processing each of the packets */
! 1007: i = sc->sc_tail;
! 1008: for (n = 0; n < MC_RXDMABUFS; n++, i++) {
! 1009: if (i == MC_RXDMABUFS)
! 1010: i = 0;
! 1011:
! 1012: cmd = &sc->sc_rxdmacmd[i];
! 1013: status = dbdma_ld16(&cmd->d_status);
! 1014: resid = dbdma_ld16(&cmd->d_resid);
! 1015:
! 1016: if ((status & DBDMA_CNTRL_ACTIVE) == 0) {
! 1017: continue;
! 1018: }
! 1019:
! 1020: count = dbdma_ld16(&cmd->d_count);
! 1021: datalen = count - resid;
! 1022: datalen -= 4; /* 4 == status bytes */
! 1023:
! 1024: if (datalen < 4 + sizeof(struct ether_header)) {
! 1025: printf("short packet len=%d\n", datalen);
! 1026: /* continue; */
! 1027: goto next;
! 1028: }
! 1029: DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0);
! 1030:
! 1031: offset = i * MACE_BUFLEN;
! 1032: statoff = offset + datalen;
! 1033: sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0];
! 1034: sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1];
! 1035: sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2];
! 1036: sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3];
! 1037: sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset;
! 1038:
! 1039: mc_rint(sc);
! 1040:
! 1041: next:
! 1042: DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS,
! 1043: DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
! 1044:
! 1045: cmd->d_status = 0;
! 1046: cmd->d_resid = 0;
! 1047: sc->sc_tail = i + 1;
! 1048: }
! 1049:
! 1050: dbdma_continue(sc->sc_rxdma);
! 1051:
! 1052: return 1;
! 1053: }
! 1054:
! 1055: void
! 1056: mc_reset_rxdma(struct mc_softc *sc)
! 1057: {
! 1058: dbdma_command_t *cmd = sc->sc_rxdmacmd;
! 1059: int i;
! 1060: u_int8_t maccc;
! 1061:
! 1062: /* Disable receiver, reset the DMA channels */
! 1063: maccc = NIC_GET(sc, MACE_MACCC);
! 1064: NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV);
! 1065:
! 1066: dbdma_reset(sc->sc_rxdma);
! 1067:
! 1068: bzero(sc->sc_rxdmacmd, 8 * sizeof(dbdma_command_t));
! 1069: for (i = 0; i < MC_RXDMABUFS; i++) {
! 1070: DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, MACE_BUFLEN,
! 1071: sc->sc_rxbuf_pa + MACE_BUFLEN * i, DBDMA_INT_ALWAYS,
! 1072: DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
! 1073: cmd++;
! 1074: }
! 1075:
! 1076: DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0,
! 1077: DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS);
! 1078: dbdma_st32(&cmd->d_cmddep, sc->sc_rxdbdma->d_paddr);
! 1079: cmd++;
! 1080:
! 1081: sc->sc_tail = 0;
! 1082:
! 1083: dbdma_start(sc->sc_rxdma, sc->sc_rxdbdma);
! 1084: /* Reenable receiver, reenable DMA */
! 1085: NIC_PUT(sc, MACE_MACCC, maccc);
! 1086: }
! 1087:
! 1088: void
! 1089: mc_reset_txdma(struct mc_softc *sc)
! 1090: {
! 1091: dbdma_command_t *cmd = sc->sc_txdmacmd;
! 1092: dbdma_regmap_t *dmareg = sc->sc_txdma;
! 1093: u_int8_t maccc;
! 1094:
! 1095: /* disable transmitter */
! 1096: maccc = NIC_GET(sc, MACE_MACCC);
! 1097: NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT);
! 1098:
! 1099: dbdma_reset(sc->sc_txdma);
! 1100:
! 1101: bzero(sc->sc_txdmacmd, 2 * sizeof(dbdma_command_t));
! 1102: DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_pa,
! 1103: DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
! 1104: cmd++;
! 1105: DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0,
! 1106: DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
! 1107:
! 1108: out32rb(&dmareg->d_cmdptrhi, 0);
! 1109: out32rb(&dmareg->d_cmdptrlo, sc->sc_txdbdma->d_paddr);
! 1110:
! 1111: /* restore old value */
! 1112: NIC_PUT(sc, MACE_MACCC, maccc);
! 1113: }
! 1114:
! 1115: /*
! 1116: * Go through the list of multicast addresses and calculate the logical
! 1117: * address filter.
! 1118: */
! 1119: void
! 1120: mace_calcladrf(struct mc_softc *sc, u_int8_t *af)
! 1121: {
! 1122: struct ether_multi *enm;
! 1123: u_int32_t crc;
! 1124: struct ifnet *ifp = &sc->sc_arpcom.ac_if;
! 1125: struct arpcom *ac = &sc->sc_arpcom;
! 1126: struct ether_multistep step;
! 1127: /*
! 1128: * Set up multicast address filter by passing all multicast addresses
! 1129: * through a crc generator, and then using the high order 6 bits as an
! 1130: * index into the 64 bit logical address filter. The high order bit
! 1131: * selects the word, while the rest of the bits select the bit within
! 1132: * the word.
! 1133: */
! 1134:
! 1135: *((u_int32_t *)af) = *((u_int32_t *)af + 1) = 0;
! 1136: ETHER_FIRST_MULTI(step, ac, enm);
! 1137: while (enm != NULL) {
! 1138: if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
! 1139: /*
! 1140: * We must listen to a range of multicast addresses.
! 1141: * For now, just accept all multicasts, rather than
! 1142: * trying to set only those filter bits needed to match
! 1143: * the range. (At this time, the only use of address
! 1144: * ranges is for IP multicast routing, for which the
! 1145: * range is big enough to require all bits set.)
! 1146: */
! 1147: goto allmulti;
! 1148: }
! 1149:
! 1150: crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo));
! 1151:
! 1152: /* Just want the 6 most significant bits. */
! 1153: crc >>= 26;
! 1154:
! 1155: /* Set the corresponding bit in the filter. */
! 1156: af[crc >> 3] |= 1 << (crc & 7);
! 1157:
! 1158: ETHER_NEXT_MULTI(step, enm);
! 1159: }
! 1160: ifp->if_flags &= ~IFF_ALLMULTI;
! 1161: return;
! 1162:
! 1163: allmulti:
! 1164: ifp->if_flags |= IFF_ALLMULTI;
! 1165: *((u_int32_t *)af) = *((u_int32_t *)af + 1) = 0xffffffff;
! 1166: }
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