Annotation of sys/arch/mac68k/include/scsi_5380.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: scsi_5380.h,v 1.3 1997/11/30 06:10:34 gene Exp $ */
! 2: /* $NetBSD: scsi_5380.h,v 1.3 1994/10/26 08:46:46 cgd Exp $ */
! 3:
! 4: /*
! 5: * Mach Operating System
! 6: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
! 7: * All Rights Reserved.
! 8: *
! 9: * Permission to use, copy, modify and distribute this software and its
! 10: * documentation is hereby granted, provided that both the copyright
! 11: * notice and this permission notice appear in all copies of the
! 12: * software, derivative works or modified versions, and any portions
! 13: * thereof, and that both notices appear in supporting documentation.
! 14: *
! 15: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
! 16: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
! 17: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 18: *
! 19: * Carnegie Mellon requests users of this software to return to
! 20: *
! 21: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
! 22: * School of Computer Science
! 23: * Carnegie Mellon University
! 24: * Pittsburgh PA 15213-3890
! 25: *
! 26: * any improvements or extensions that they make and grant Carnegie the
! 27: * rights to redistribute these changes.
! 28: */
! 29: /*
! 30: * File: scsi_5380.h
! 31: * Author: Alessandro Forin, Carnegie Mellon University
! 32: * Date: 5/91
! 33: *
! 34: * Defines for the NCR 5380 (SCSI chip), aka Am5380
! 35: */
! 36:
! 37: #ifndef _MAC68K_SCSI5380_H_
! 38: #define _MAC68K_SCSI5380_H_
! 39:
! 40: /*
! 41: * Register map
! 42: */
! 43:
! 44: typedef struct {
! 45: volatile unsigned char sci_data; /* r: Current data */
! 46: #define sci_odata sci_data /* w: Out data */
! 47: PAD(pad0);
! 48:
! 49: volatile unsigned char sci_icmd; /* rw: Initiator command */
! 50: PAD(pad1);
! 51:
! 52: volatile unsigned char sci_mode; /* rw: Mode */
! 53: PAD(pad2);
! 54:
! 55: volatile unsigned char sci_tcmd; /* rw: Target command */
! 56: PAD(pad3);
! 57:
! 58: volatile unsigned char sci_bus_csr; /* r: Bus Status */
! 59: #define sci_sel_enb sci_bus_csr /* w: Select enable */
! 60: PAD(pad4);
! 61:
! 62: volatile unsigned char sci_csr; /* r: Status */
! 63: #define sci_dma_send sci_csr /* w: Start dma send data */
! 64: PAD(pad5);
! 65:
! 66: volatile unsigned char sci_idata; /* r: Input data */
! 67: #define sci_trecv sci_idata /* w: Start dma receive, target */
! 68: PAD(pad6);
! 69:
! 70: volatile unsigned char sci_iack; /* r: Interrupt Acknowledge */
! 71: #define sci_irecv sci_iack /* w: Start dma receive, initiator */
! 72: } sci_regmap_t;
! 73:
! 74:
! 75: /*
! 76: * Initiator command register
! 77: */
! 78:
! 79: #define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */
! 80: #define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */
! 81: #define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */
! 82: #define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */
! 83: #define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */
! 84: #define SCI_ICMD_LST 0x20 /* r: Lost arbitration */
! 85: #define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */
! 86: #define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */
! 87: #define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */
! 88: #define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */
! 89:
! 90:
! 91: /*
! 92: * Mode register
! 93: */
! 94:
! 95: #define SCI_MODE_ARB 0x01 /* rw: Start arbitration */
! 96: #define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */
! 97: #define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */
! 98: #define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */
! 99: #define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */
! 100: #define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */
! 101: #define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */
! 102: #define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake (MBZ) */
! 103:
! 104:
! 105: /*
! 106: * Target command register
! 107: */
! 108:
! 109: #define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */
! 110: #define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */
! 111: #define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */
! 112: #define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */
! 113: #define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */
! 114: #define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred
! 115: * (not on 5380/1) */
! 116:
! 117: #define SCI_PHASE(x) SCSI_PHASE(x)
! 118:
! 119: /*
! 120: * Current (SCSI) Bus status
! 121: */
! 122:
! 123: #define SCI_BUS_DBP 0x01 /* r: Data Bus parity */
! 124: #define SCI_BUS_SEL 0x02 /* r: SEL signal */
! 125: #define SCI_BUS_IO 0x04 /* r: I/O signal */
! 126: #define SCI_BUS_CD 0x08 /* r: C/D signal */
! 127: #define SCI_BUS_MSG 0x10 /* r: MSG signal */
! 128: #define SCI_BUS_REQ 0x20 /* r: REQ signal */
! 129: #define SCI_BUS_BSY 0x40 /* r: BSY signal */
! 130: #define SCI_BUS_RST 0x80 /* r: RST signal */
! 131:
! 132: #define SCI_CUR_PHASE(x) SCSI_PHASE((x)>>2)
! 133:
! 134: /*
! 135: * Bus and Status register
! 136: */
! 137:
! 138: #define SCI_CSR_ACK 0x01 /* r: ACK signal */
! 139: #define SCI_CSR_ATN 0x02 /* r: ATN signal */
! 140: #define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */
! 141: #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
! 142: #define SCI_CSR_INT 0x10 /* r: Interrupt request */
! 143: #define SCI_CSR_PERR 0x20 /* r: Parity error */
! 144: #define SCI_CSR_DREQ 0x40 /* r: DMA request */
! 145: #define SCI_CSR_DONE 0x80 /* r: DMA count is zero */
! 146:
! 147: #endif /* _MAC68K_SCSI5380_H_ */
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