Annotation of sys/arch/mac68k/dev/zsvar.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: zsvar.h,v 1.4 2003/06/02 23:27:49 millert Exp $ */
! 2: /* $NetBSD: zsvar.h,v 1.2 1995/12/13 03:08:12 briggs Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1994 Gordon W. Ross
! 6: * Copyright (c) 1992, 1993
! 7: * The Regents of the University of California. All rights reserved.
! 8: *
! 9: * This software was developed by the Computer Systems Engineering group
! 10: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
! 11: * contributed to Berkeley.
! 12: *
! 13: * All advertising materials mentioning features or use of this software
! 14: * must display the following acknowledgement:
! 15: * This product includes software developed by the University of
! 16: * California, Lawrence Berkeley Laboratory.
! 17: *
! 18: * Redistribution and use in source and binary forms, with or without
! 19: * modification, are permitted provided that the following conditions
! 20: * are met:
! 21: * 1. Redistributions of source code must retain the above copyright
! 22: * notice, this list of conditions and the following disclaimer.
! 23: * 2. Redistributions in binary form must reproduce the above copyright
! 24: * notice, this list of conditions and the following disclaimer in the
! 25: * documentation and/or other materials provided with the distribution.
! 26: * 3. Neither the name of the University nor the names of its contributors
! 27: * may be used to endorse or promote products derived from this software
! 28: * without specific prior written permission.
! 29: *
! 30: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 31: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 32: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 33: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 34: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 35: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 36: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 37: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 38: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 39: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 40: * SUCH DAMAGE.
! 41: *
! 42: * @(#)zsvar.h 8.1 (Berkeley) 6/11/93
! 43: */
! 44:
! 45: /*
! 46: * Software state, per zs channel.
! 47: *
! 48: * The zs chip has insufficient buffering, so we provide a software
! 49: * buffer using a two-level interrupt scheme. The hardware (high priority)
! 50: * interrupt simply grabs the `cause' of the interrupt and stuffs it into
! 51: * a ring buffer. It then schedules a software interrupt; the latter
! 52: * empties the ring as fast as it can, hoping to avoid overflow.
! 53: *
! 54: * Interrupts can happen because of:
! 55: * - received data;
! 56: * - transmit pseudo-DMA done; and
! 57: * - status change.
! 58: * These are all stored together in the (single) ring. The size of the
! 59: * ring is a power of two, to make % operations fast. Since we need two
! 60: * bits to distinguish the interrupt type, and up to 16 for the received
! 61: * data plus RR1 status, we use 32 bits per ring entry.
! 62: *
! 63: * When the value is a character + RR1 status, the character is in the
! 64: * upper 8 bits of the RR1 status.
! 65: */
! 66: #define ZLRB_RING_SIZE 512 /* ZS line ring buffer size */
! 67: #define ZLRB_RING_MASK 511 /* mask for same */
! 68:
! 69: /* 0 is reserved (means "no interrupt") */
! 70: #define ZRING_RINT 1 /* receive data interrupt */
! 71: #define ZRING_XINT 2 /* transmit done interrupt */
! 72: #define ZRING_SINT 3 /* status change interrupt */
! 73:
! 74: #define ZRING_TYPE(x) ((x) & 3)
! 75: #define ZRING_VALUE(x) ((x) >> 8)
! 76: #define ZRING_MAKE(t, v) ((t) | (v) << 8)
! 77:
! 78: struct zs_chanstate {
! 79: struct zs_chanstate *cs_next; /* linked list for zshard() */
! 80: volatile struct zschan *cs_zc; /* points to hardware regs */
! 81: int cs_unit; /* unit number */
! 82: struct tty *cs_ttyp; /* ### */
! 83:
! 84: /*
! 85: * We must keep a copy of the write registers as they are
! 86: * mostly write-only and we sometimes need to set and clear
! 87: * individual bits (e.g., in WR3). Not all of these are
! 88: * needed but 16 bytes is cheap and this makes the addressing
! 89: * simpler. Unfortunately, we can only write to some registers
! 90: * when the chip is not actually transmitting, so whenever
! 91: * we are expecting a `transmit done' interrupt the preg array
! 92: * is allowed to `get ahead' of the current values. In a
! 93: * few places we must change the current value of a register,
! 94: * rather than (or in addition to) the pending value; for these
! 95: * cs_creg[] contains the current value.
! 96: */
! 97: u_char cs_creg[16]; /* current values */
! 98: u_char cs_preg[16]; /* pending values */
! 99: u_char cs_heldchange; /* change pending (creg != preg) */
! 100: u_char cs_rr0; /* last rr0 processed */
! 101: u_char cs_rr0_mask; /* xor mask for inverted status bits */
! 102: u_char cs_SFC; /* do Software-based CTS Flow Control? */
! 103: u_char cs_holdSFC; /* Are we holding transmission for CTS to assert? */
! 104: u_char cs_tiu; /* transmitter in use (char. being sent) */
! 105:
! 106: /* pure software data, per channel */
! 107: char cs_softcar; /* software carrier */
! 108: char cs_conk; /* is console keyboard, decode L1-A */
! 109: char cs_brkabort; /* abort (as if via L1-A) on BREAK */
! 110: char cs_kgdb; /* enter debugger on frame char */
! 111: char cs_consio; /* port does /dev/console I/O */
! 112: char cs_xxx; /* (spare) */
! 113: int cs_speed; /* default baud rate (from ROM) */
! 114:
! 115: /*
! 116: * The transmit byte count and address are used for pseudo-DMA
! 117: * output in the hardware interrupt code. PDMA can be suspended
! 118: * to get pending changes done; heldtbc is used for this. It can
! 119: * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state.
! 120: */
! 121: int cs_tbc; /* transmit byte count */
! 122: caddr_t cs_tba; /* transmit buffer address */
! 123: int cs_heldtbc; /* held tbc while xmission stopped */
! 124:
! 125: /*
! 126: * Printing an overrun error message often takes long enough to
! 127: * cause another overrun, so we only print one per second.
! 128: */
! 129: long cs_rotime; /* time of last ring overrun */
! 130: long cs_fotime; /* time of last fifo overrun */
! 131:
! 132: /*
! 133: * The ring buffer.
! 134: */
! 135: u_int cs_rbget; /* ring buffer `get' index */
! 136: volatile u_int cs_rbput; /* ring buffer `put' index */
! 137: long cs_rbuf[ZLRB_RING_SIZE];/* type, value pairs */
! 138: };
! 139:
! 140: /*
! 141: * N.B.: the keyboard is channel 1, the mouse channel 0; ttyb is 1, ttya
! 142: * is 0. In other words, the things are BACKWARDS.
! 143: */
! 144: #define ZS_CHAN_A 1
! 145: #define ZS_CHAN_B 0
! 146:
! 147: /*
! 148: * Macros to read and write individual registers (except 0) in a channel.
! 149: * The ZS chip requires a 1.6 uSec. recovery time between accesses.
! 150: */
! 151: #define ZS_READ(c, r) zs_read(c, r)
! 152: #define ZS_WRITE(c, r, v) zs_write(c, r, v)
! 153: #define ZS_DELAY() delay2us()
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