Annotation of sys/arch/mac68k/dev/z8530sc.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: z8530sc.h,v 1.6 2004/11/25 18:32:10 miod Exp $ */
2: /* $NetBSD: z8530sc.h,v 1.5 1996/12/17 20:42:42 gwr Exp $ */
3:
4: /*
5: * Copyright (c) 1994 Gordon W. Ross
6: * Copyright (c) 1992, 1993
7: * The Regents of the University of California. All rights reserved.
8: *
9: * This software was developed by the Computer Systems Engineering group
10: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11: * contributed to Berkeley.
12: *
13: * All advertising materials mentioning features or use of this software
14: * must display the following acknowledgement:
15: * This product includes software developed by the University of
16: * California, Lawrence Berkeley Laboratory.
17: *
18: * Redistribution and use in source and binary forms, with or without
19: * modification, are permitted provided that the following conditions
20: * are met:
21: * 1. Redistributions of source code must retain the above copyright
22: * notice, this list of conditions and the following disclaimer.
23: * 2. Redistributions in binary form must reproduce the above copyright
24: * notice, this list of conditions and the following disclaimer in the
25: * documentation and/or other materials provided with the distribution.
26: * 3. Neither the name of the University nor the names of its contributors
27: * may be used to endorse or promote products derived from this software
28: * without specific prior written permission.
29: *
30: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40: * SUCH DAMAGE.
41: *
42: * @(#)zsvar.h 8.1 (Berkeley) 6/11/93
43: */
44:
45:
46: /*
47: * Software state, per zs channel.
48: */
49: struct zs_chanstate {
50:
51: /* Pointers to the device registers. */
52: volatile u_char *cs_reg_csr; /* ctrl, status, and reg. number. */
53: volatile u_char *cs_reg_data; /* data or numbered register */
54:
55: int cs_channel; /* sub-unit number */
56: void *cs_private; /* sub-driver data pointer */
57: struct zsops *cs_ops;
58:
59: int cs_brg_clk; /* BAUD Rate Generator clock
60: * (usually PCLK / 16) */
61: int cs_defspeed; /* default baud rate */
62: int cs_defcflag; /* default cflag */
63:
64: /*
65: * We must keep a copy of the write registers as they are
66: * mostly write-only and we sometimes need to set and clear
67: * individual bits (e.g., in WR3). Not all of these are
68: * needed but 16 bytes is cheap and this makes the addressing
69: * simpler. Unfortunately, we can only write to some registers
70: * when the chip is not actually transmitting, so whenever
71: * we are expecting a `transmit done' interrupt the preg array
72: * is allowed to `get ahead' of the current values. In a
73: * few places we must change the current value of a register,
74: * rather than (or in addition to) the pending value; for these
75: * cs_creg[] contains the current value.
76: */
77: u_char cs_creg[16]; /* current values */
78: u_char cs_preg[16]; /* pending values */
79: int cs_heldchange; /* change pending (creg != preg) */
80:
81: u_char cs_rr0; /* last rr0 processed */
82: u_char cs_rr0_delta; /* rr0 changes at status intr. */
83: u_char cs_rr0_dcd; /* which bit to read as DCD */
84: u_char cs_rr0_cts; /* which bit to read as CTS */
85: /* the above is set only while CRTSCTS is enabled. */
86:
87: u_char cs_wr5_dtr; /* which bit to write as DTR */
88: u_char cs_wr5_rts; /* which bit to write as RTS */
89: /* the above is set only while CRTSCTS is enabled. */
90:
91: char cs_softreq; /* need soft interrupt call */
92: char cs_pad[1];
93: /* MD code might define a larger variant of this. */
94: };
95:
96: /*
97: * Function vector - per channel
98: */
99: struct zs_chanstate;
100: typedef void (*zsop_t) (struct zs_chanstate *);
101: struct zsops {
102: zsop_t zsop_rxint; /* receive char available */
103: zsop_t zsop_stint; /* external/status */
104: zsop_t zsop_txint; /* xmit buffer empty */
105: zsop_t zsop_softint; /* process software interrupt */
106: };
107:
108: extern struct zsops zsops_null;
109:
110: struct zsc_attach_args {
111: int channel; /* two serial channels per zsc */
112: int hwflags;
113: };
114: #define ZS_HWFLAG_CONSOLE 1
115: #define ZS_HWFLAG_NO_DCD 2 /* Ignore the DCD bit */
116: #define ZS_HWFLAG_NO_CTS 4 /* Ignore the CTS bit */
117: #define ZS_HWFLAG_RAW 8 /* advise raw mode */
118:
119: int zsc_intr_hard(void *);
120: int zsc_intr_soft(void *);
121:
122: void zs_abort(struct zs_chanstate *);
123: void zs_break(struct zs_chanstate *, int);
124: void zs_iflush (struct zs_chanstate *);
125: void zs_loadchannelregs(struct zs_chanstate *);
126: int zs_set_speed (struct zs_chanstate *, int);
127: int zs_set_modes (struct zs_chanstate *, int);
128: int zs_getspeed(struct zs_chanstate *);
129:
130: extern int zs_major;
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