Annotation of sys/arch/mac68k/dev/ncr5380reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ncr5380reg.h,v 1.6 2006/01/16 21:45:58 miod Exp $ */
2: /* $NetBSD: ncr5380reg.h,v 1.9 1996/05/05 06:16:58 briggs Exp $ */
3:
4: /*
5: * Copyright (c) 1995 Leo Weppelman.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by Leo Weppelman.
19: * 4. The name of the author may not be used to endorse or promote products
20: * derived from this software without specific prior written permission
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32: */
33:
34: #ifndef _NCR5380REG_H
35: #define _NCR5380REG_H
36: /*
37: * NCR5380 common interface definitions.
38: */
39:
40: /*
41: * Register numbers: (first argument to GET/SET_5380_REG )
42: */
43: #define NCR5380_DATA 0 /* Data register */
44: #define NCR5380_ICOM 1 /* Initiator command register */
45: #define NCR5380_MODE 2 /* Mode register */
46: #define NCR5380_TCOM 3 /* Target command register */
47: #define NCR5380_IDSTAT 4 /* Bus status register */
48: #define NCR5380_DMSTAT 5 /* DMA status register */
49: #define NCR5380_TRCV 6 /* Target receive register */
50: #define NCR5380_IRCV 7 /* Initiator receive register */
51:
52: /*
53: * Definitions for Initiator command register.
54: */
55: #define SC_A_RST 0x80 /* RW - Assert RST */
56: #define SC_TEST 0x40 /* W - Test mode */
57: #define SC_AIP 0x40 /* R - Arbitration in progress */
58: #define SC_LA 0x20 /* R - Lost arbitration */
59: #define SC_A_ACK 0x10 /* RW - Assert ACK */
60: #define SC_A_BSY 0x08 /* RW - Assert BSY */
61: #define SC_A_SEL 0x04 /* RW - Assert SEL */
62: #define SC_A_ATN 0x02 /* RW - Assert ATN */
63: #define SC_ADTB 0x01 /* RW - Assert Data To Bus */
64:
65: /*
66: * Definitions for mode register
67: */
68: #define SC_B_DMA 0x80 /* RW - Block mode DMA (not on TT!) */
69: #define SC_T_MODE 0x40 /* RW - Target mode */
70: #define SC_E_PAR 0x20 /* RW - Enable parity check */
71: #define SC_E_PARI 0x10 /* RW - Enable parity interrupt */
72: #define SC_E_EOPI 0x08 /* RW - Enable End Of Process Interrupt */
73: #define SC_MON_BSY 0x04 /* RW - Monitor BSY */
74: #define SC_M_DMA 0x02 /* RW - Set DMA mode */
75: #define SC_ARBIT 0x01 /* RW - Arbitrate */
76:
77: /*
78: * Definitions for tcom register
79: */
80: #define SC_LBS 0x80 /* RW - Last Byte Send (not on TT!) */
81: #define SC_A_REQ 0x08 /* RW - Assert REQ */
82: #define SC_A_MSG 0x04 /* RW - Assert MSG */
83: #define SC_A_CD 0x02 /* RW - Assert C/D */
84: #define SC_A_IO 0x01 /* RW - Assert I/O */
85:
86: /*
87: * Definitions for idstat register
88: */
89: #define SC_S_RST 0x80 /* R - RST is set */
90: #define SC_S_BSY 0x40 /* R - BSY is set */
91: #define SC_S_REQ 0x20 /* R - REQ is set */
92: #define SC_S_MSG 0x10 /* R - MSG is set */
93: #define SC_S_CD 0x08 /* R - C/D is set */
94: #define SC_S_IO 0x04 /* R - I/O is set */
95: #define SC_S_SEL 0x02 /* R - SEL is set */
96: #define SC_S_PAR 0x01 /* R - Parity bit */
97:
98: /*
99: * Definitions for dmastat register
100: */
101: #define SC_END_DMA 0x80 /* R - End of DMA */
102: #define SC_DMA_REQ 0x40 /* R - DMA request */
103: #define SC_PAR_ERR 0x20 /* R - Parity error */
104: #define SC_IRQ_SET 0x10 /* R - IRQ is active */
105: #define SC_PHS_MTCH 0x08 /* R - Phase Match */
106: #define SC_BSY_ERR 0x04 /* R - Busy error */
107: #define SC_ATN_STAT 0x02 /* R - State of ATN line */
108: #define SC_ACK_STAT 0x01 /* R - State of ACK line */
109: #define SC_S_SEND 0x00 /* W - Start DMA output */
110:
111: #define SC_CLINT { /* Clear interrupts */ \
112: int i = GET_5380_REG(NCR5380_IRCV); \
113: }
114:
115:
116: /*
117: * Definition of SCSI-bus phases. The values are determined by signals
118: * on the SCSI-bus. DO NOT CHANGE!
119: * The values must be used to index the pointers in SCSI-PARMS.
120: */
121: #define NR_PHASE 8
122: #define PH_DATAOUT 0
123: #define PH_DATAIN 1
124: #define PH_CMD 2
125: #define PH_STATUS 3
126: #define PH_RES1 4
127: #define PH_RES2 5
128: #define PH_MSGOUT 6
129: #define PH_MSGIN 7
130:
131: #define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
132: #define PH_IN(phase) (phase & 1) /* TRUE if input phase */
133:
134: /*
135: * Id of Host-adapter
136: */
137: #define SC_HOST_ID 0x80
138:
139: /*
140: * Base setting for 5380 mode register
141: */
142: #define IMODE_BASE SC_E_PAR
143:
144: /*
145: * SCSI completion status codes, should move to sys/scsi/????
146: */
147: #define SCSMASK 0x1e /* status code mask */
148: #define SCSGOOD 0x00 /* good status */
149: #define SCSCHKC 0x02 /* check condition */
150: #define SCSBUSY 0x08 /* busy status */
151: #define SCSCMET 0x04 /* condition met / good */
152:
153: /*
154: * Return values of check_intr()
155: */
156: #define INTR_SPURIOUS 0
157: #define INTR_RESEL 2
158: #define INTR_DMA 3
159:
160: struct ncr_softc {
161: struct device sc_dev;
162: struct scsi_link sc_link;
163:
164: struct via2hand sc_ih_irq, sc_ih_drq;
165:
166: /*
167: * Some (pre-SCSI2) devices don't support select with ATN.
168: * If the device responds to select with ATN by going into
169: * command phase (ignoring ATN), then we flag it in the
170: * following bitmask.
171: * We also keep track of which devices have been selected
172: * before. This allows us to not even try raising ATN if
173: * the target doesn't respond to it the first time.
174: */
175: u_int8_t sc_noselatn;
176: u_int8_t sc_selected;
177: };
178:
179: /*
180: * Max. number of dma-chains per request
181: */
182: #define MAXDMAIO (MAXPHYS/NBPG + 1)
183:
184: /*
185: * Some requests are not contiguous in physical memory. We need to break them
186: * up into contiguous parts for DMA.
187: */
188: struct dma_chain {
189: u_int dm_count;
190: u_long dm_addr;
191: };
192:
193: /*
194: * Define our issue, free and disconnect queue's.
195: */
196: typedef struct req_q {
197: struct req_q *next; /* next in free, issue or discon queue */
198: struct req_q *link; /* next linked command to execute */
199: struct scsi_xfer *xs; /* request from high-level driver */
200: u_short dr_flag; /* driver state */
201: u_char phase; /* current SCSI phase */
202: u_char msgout; /* message to send when requested */
203: u_char targ_id; /* target for command */
204: u_char targ_lun; /* lun for command */
205: u_char status; /* returned status byte */
206: u_char message; /* returned message byte */
207: u_char *bounceb; /* allocated bounce buffer */
208: u_char *bouncerp; /* bounce read-pointer */
209: struct dma_chain dm_chain[MAXDMAIO];
210: struct dma_chain *dm_cur; /* current dma-request */
211: struct dma_chain *dm_last; /* last dma-request */
212: long xdata_len; /* length of transfer */
213: u_char *xdata_ptr; /* virtual address of transfer */
214: struct scsi_generic xcmd; /* command to execute */
215: } SC_REQ;
216:
217: /*
218: * Values for dr_flag:
219: */
220: #define DRIVER_IN_DMA 0x01 /* Non-polled DMA activated */
221: #define DRIVER_AUTOSEN 0x02 /* Doing automatic sense */
222: #define DRIVER_NOINT 0x04 /* We are booting: no interrupts */
223: #define DRIVER_DMAOK 0x08 /* DMA can be used on this request */
224: #define DRIVER_BOUNCING 0x10 /* Using the bounce buffer */
225: #define DRIVER_LINKCHK 0x20 /* Doing the linked command check */
226:
227: /* XXX: Should go to ncr5380var.h */
228: static SC_REQ *issue_q = NULL; /* Commands waiting to be issued*/
229: static SC_REQ *discon_q = NULL; /* Commands disconnected */
230: static SC_REQ *connected = NULL; /* Command currently connected */
231:
232: /*
233: * Function decls:
234: */
235: static int transfer_pio(u_char *, u_char *, u_long *, int);
236: static int wait_req_true(void);
237: static int wait_req_false(void);
238: static int scsi_select(SC_REQ *, int);
239: static int handle_message(SC_REQ *, u_int);
240: static void ack_message(void);
241: static void nack_message(SC_REQ *, u_char);
242: static void finish_req(SC_REQ *reqp);
243: static int command_size(u_char opcode);
244: static int information_transfer(struct ncr_softc *);
245: static void reselect(struct ncr_softc *);
246: static int check_autosense(SC_REQ *, int);
247: static int reach_msg_out(struct ncr_softc *, u_long);
248: static int check_intr(struct ncr_softc *);
249: static void scsi_reset(void);
250: static void scsi_reset_verbose(struct ncr_softc *, const char *);
251: static void run_main(struct ncr_softc *);
252: static void scsi_main(struct ncr_softc *);
253: static void ncr_ctrl_intr(struct ncr_softc *);
254: static void ncr_tprint(SC_REQ *, char *, ...);
255: static void ncr_aprint(struct ncr_softc *, char *, ...);
256:
257: static void show_data_sense(struct scsi_xfer *xs);
258: static void show_request(SC_REQ *, char *);
259: /* static void show_phase(SC_REQ *, int); */
260: static void show_signals(u_char, u_char);
261:
262: #endif /* _NCR5380REG_H */
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