Annotation of sys/arch/mac68k/dev/if_snreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_snreg.h,v 1.4 2001/07/04 08:52:46 niklas Exp $ */
2: /* $NetBSD: if_snreg.h,v 1.3 1997/04/30 19:47:12 scottr Exp $ */
3:
4: /*
5: * Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk)
6: * You may use, copy, and modify this program so long as you retain the
7: * copyright line.
8: */
9:
10: /*
11: * if_snreg.h -- National Semiconductor DP8393X (SONIC) register defs
12: */
13:
14: /*
15: * SONIC registers as seen by the processor
16: */
17: #define SNR_CR 0x00 /* Command */
18: #define SNR_DCR 0x01 /* Data Configuration */
19: #define SNR_RCR 0x02 /* Receive Control */
20: #define SNR_TCR 0x03 /* Transmit Control */
21: #define SNR_IMR 0x04 /* Interrupt Mask */
22: #define SNR_ISR 0x05 /* Interrupt Status */
23: #define SNR_UTDA 0x06 /* Upper Transmit Descriptor Address */
24: #define SNR_CTDA 0x07 /* Current Transmit Descriptor Address */
25: #define SNR_TPS 0x08 /* Transmit Packet Size */
26: #define SNR_TFC 0x09 /* Transmit Fragment Count */
27: #define SNR_TSA0 0x0a /* Transmit Start Address 0 */
28: #define SNR_TSA1 0x0b /* Transmit Start Address 1 */
29: #define SNR_TFS 0x0c /* Transmit Fragment Size */
30: #define SNR_URDA 0x0d /* Upper Receive Descriptor Address */
31: #define SNR_CRDA 0x0e /* Current Receive Descriptor Address */
32: #define SNR_CRBA0 0x0f /* Current Receive Buffer Address 0 */
33: #define SNR_CRBA1 0x10 /* Current Receive Buffer Address 1 */
34: #define SNR_RBWC0 0x11 /* Remaining Buffer Word Count 0 */
35: #define SNR_RBWC1 0x12 /* Remaining Buffer Word Count 1 */
36: #define SNR_EOBC 0x13 /* End Of Buffer Word Count */
37: #define SNR_URRA 0x14 /* Upper Receive Resource Address */
38: #define SNR_RSA 0x15 /* Resource Start Address */
39: #define SNR_REA 0x16 /* Resource End Address */
40: #define SNR_RRP 0x17 /* Resource Read Pointer */
41: #define SNR_RWP 0x18 /* Resource Write Pointer */
42: #define SNR_TRBA0 0x19 /* Temporary Receive Buffer Address 0 */
43: #define SNR_TRBA1 0x1a /* Temporary Receive Buffer Address 1 */
44: #define SNR_TBWC0 0x1b /* Temporary Buffer Word Count 0 */
45: #define SNR_TBWC1 0x1c /* Temporary Buffer Word Count 1 */
46: #define SNR_ADDR0 0x1d /* Address Generator 0 */
47: #define SNR_ADDR1 0x1e /* Address Generator 1 */
48: #define SNR_LLFA 0x1f /* Last Link Field Address */
49: #define SNR_TTDA 0x20 /* Temp Transmit Descriptor Address */
50: #define SNR_CEP 0x21 /* CAM Entry Pointer */
51: #define SNR_CAP2 0x22 /* CAM Address Port 2 */
52: #define SNR_CAP1 0x23 /* CAM Address Port 1 */
53: #define SNR_CAP0 0x24 /* CAM Address Port 0 */
54: #define SNR_CE 0x25 /* CAM Enable */
55: #define SNR_CDP 0x26 /* CAM Descriptor Pointer */
56: #define SNR_CDC 0x27 /* CAM Descriptor Count */
57: #define SNR_SR 0x28 /* Silicon Revision */
58: #define SNR_WT0 0x29 /* Watchdog Timer 0 */
59: #define SNR_WT1 0x2a /* Watchdog Timer 1 */
60: #define SNR_RSC 0x2b /* Receive Sequence Counter */
61: #define SNR_CRCT 0x2c /* CRC Error Tally */
62: #define SNR_FAET 0x2d /* FAE Tally */
63: #define SNR_MPT 0x2e /* Missed Packet Tally */
64: #define SNR_MDT 0x2f /* Maximum Deferral Timer */
65: #define SNR_RTC 0x30 /* Receive Test Control */
66: #define SNR_TTC 0x31 /* Transmit Test Control */
67: #define SNR_DTC 0x32 /* DMA Test Control */
68: #define SNR_CC0 0x33 /* CAM Comparison 0 */
69: #define SNR_CC1 0x34 /* CAM Comparison 1 */
70: #define SNR_CC2 0x35 /* CAM Comparison 2 */
71: #define SNR_CM 0x36 /* CAM Match */
72: #define SNR_RES1 0x37 /* reserved */
73: #define SNR_RES2 0x38 /* reserved */
74: #define SNR_RBC 0x39 /* Receiver Byte Count */
75: #define SNR_RES3 0x3a /* reserved */
76: #define SNR_TBO 0x3b /* Transmitter Backoff Counter */
77: #define SNR_TRC 0x3c /* Transmitter Random Counter */
78: #define SNR_TBM 0x3d /* Transmitter Backoff Mask */
79: #define SNR_RES4 0x3e /* Reserved */
80: #define SNR_DCR2 0x3f /* Data Configuration 2 (AVF) */
81:
82: #define SN_NREGS 0x40
83:
84: /*
85: * Register Interpretations
86: */
87:
88: /*
89: * The command register is used for issuing commands to the SONIC.
90: * With the exception of CR_RST, the bit is reset when the operation
91: * completes.
92: */
93: #define CR_LCAM 0x0200 /* load CAM with descriptor at s_cdp */
94: #define CR_RRRA 0x0100 /* read next RRA descriptor at s_rrp */
95: #define CR_RST 0x0080 /* software reset */
96: #define CR_ST 0x0020 /* start timer */
97: #define CR_STP 0x0010 /* stop timer */
98: #define CR_RXEN 0x0008 /* receiver enable */
99: #define CR_RXDIS 0x0004 /* receiver disable */
100: #define CR_TXP 0x0002 /* transmit packets */
101: #define CR_HTX 0x0001 /* halt transmission */
102:
103: /*
104: * The data configuration register establishes the SONIC's bus cycle
105: * operation. This register can only be accessed when the SONIC is in
106: * reset mode (s_cr.CR_RST is set.)
107: */
108: #define DCR_EXBUS 0x8000 /* extended bus mode (AVF) */
109: #define DCR_LBR 0x2000 /* latched bus retry */
110: #define DCR_PO1 0x1000 /* programmable output 1 */
111: #define DCR_PO0 0x0800 /* programmable output 0 */
112: #define DCR_STERM 0x0400 /* synchronous termination */
113: #define DCR_USR1 0x0200 /* reflects USR1 input pin */
114: #define DCR_USR0 0x0100 /* reflects USR0 input pin */
115: #define DCR_WC1 0x0080 /* wait state control 1 */
116: #define DCR_WC0 0x0040 /* wait state control 0 */
117: #define DCR_DW 0x0020 /* data width select */
118: #define DCR_BMS 0x0010 /* DMA block mode select */
119: #define DCR_RFT1 0x0008 /* receive FIFO threshold control 1 */
120: #define DCR_RFT0 0x0004 /* receive FIFO threshold control 0 */
121: #define DCR_TFT1 0x0002 /* transmit FIFO threshold control 1 */
122: #define DCR_TFT0 0x0001 /* transmit FIFO threshold control 0 */
123:
124: /* data configuration register aliases */
125: #define DCR_SYNC DCR_STERM /* synchronous (memory cycle 2 clocks) */
126: #define DCR_ASYNC 0 /* asynchronous (memory cycle 3 clocks) */
127:
128: #define DCR_WAIT0 0 /* 0 wait states added */
129: #define DCR_WAIT1 DCR_WC0 /* 1 wait state added */
130: #define DCR_WAIT2 DCR_WC1 /* 2 wait states added */
131: #define DCR_WAIT3 (DCR_WC1|DCR_WC0) /* 3 wait states added */
132:
133: #define DCR_DW16 0 /* use 16-bit DMA accesses */
134: #define DCR_DW32 DCR_DW /* use 32-bit DMA accesses */
135:
136: #define DCR_DMAEF 0 /* DMA until TX/RX FIFO has emptied/filled */
137: #define DCR_DMABLOCK DCR_BMS /* DMA until RX/TX threshold crossed */
138:
139: #define DCR_RFT4 0 /* receive threshold 4 bytes */
140: #define DCR_RFT8 DCR_RFT0 /* receive threshold 8 bytes */
141: #define DCR_RFT16 DCR_RFT1 /* receive threshold 16 bytes */
142: #define DCR_RFT24 (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */
143:
144: #define DCR_TFT8 0 /* transmit threshold 8 bytes */
145: #define DCR_TFT16 DCR_TFT0 /* transmit threshold 16 bytes */
146: #define DCR_TFT24 DCR_TFT1 /* transmit threshold 24 bytes */
147: #define DCR_TFT28 (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */
148:
149: /*
150: * The receive control register is used to filter incoming packets and
151: * provides status information on packets received.
152: * The contents of the register are copied into the RXpkt.status field
153: * when a packet is received. RCR_MC - RCR_PRX are then reset.
154: */
155: #define RCR_ERR 0x8000 /* accept packets with CRC errors */
156: #define RCR_RNT 0x4000 /* accept runt (length < 64) packets */
157: #define RCR_BRD 0x2000 /* accept broadcast packets */
158: #define RCR_PRO 0x1000 /* accept all physical address packets */
159: #define RCR_AMC 0x0800 /* accept all multicast packets */
160: #define RCR_LB1 0x0400 /* loopback control 1 */
161: #define RCR_LB0 0x0200 /* loopback control 0 */
162: #define RCR_MC 0x0100 /* multicast packet received */
163: #define RCR_BC 0x0080 /* broadcast packet received */
164: #define RCR_LPKT 0x0040 /* last packet in RBA (RBWC < EOBC) */
165: #define RCR_CRS 0x0020 /* carrier sense activity */
166: #define RCR_COL 0x0010 /* collision activity */
167: #define RCR_CRC 0x0008 /* CRC error */
168: #define RCR_FAE 0x0004 /* frame alignment error */
169: #define RCR_LBK 0x0002 /* loopback packet received */
170: #define RCR_PRX 0x0001 /* packet received without errors */
171:
172: /* receiver control register aliases */
173: /* the loopback control bits provide the following options */
174: #define RCR_LBNONE 0 /* no loopback - normal operation */
175: #define RCR_LBMAC RCR_LB0 /* MAC loopback */
176: #define RCR_LBENDEC RCR_LB1 /* ENDEC loopback */
177: #define RCR_LBTRANS (RCR_LB1|RCR_LB0) /* transceiver loopback */
178:
179: /*
180: * The transmit control register controls the SONIC's transmit operations.
181: * TCR_PINT - TCR_EXDIS are loaded from the TXpkt.config field at the
182: * start of transmission. TCR_EXD-TCR_PTX are cleared at the beginning
183: * of transmission and updated when the transmission is completed.
184: */
185: #define TCR_PINT 0x8000 /* interrupt when transmission starts */
186: #define TCR_POWC 0x4000 /* program out of window collision timer */
187: #define TCR_CRCI 0x2000 /* transmit packet without 4 byte FCS */
188: #define TCR_EXDIS 0x1000 /* disable excessive deferral timer */
189: #define TCR_EXD 0x0400 /* excessive deferrals occurred (>3.2ms) */
190: #define TCR_DEF 0x0200 /* deferred transmissions occurred */
191: #define TCR_NCRS 0x0100 /* carrier not present during transmission */
192: #define TCR_CRSL 0x0080 /* carrier lost during transmission */
193: #define TCR_EXC 0x0040 /* excessive collisions (>16) detected */
194: #define TCR_OWC 0x0020 /* out of window (bad) collision occurred */
195: #define TCR_PMB 0x0008 /* packet monitored bad - the tansmitted
196: * packet had a bad source address or CRC */
197: #define TCR_FU 0x0004 /* FIFO underrun (memory access failed) */
198: #define TCR_BCM 0x0002 /* byte count mismatch (TXpkt.pkt_size
199: * != sum(TXpkt.frag_size) */
200: #define TCR_PTX 0x0001 /* packet transmitted without errors */
201: #define TCR_NC 0xf000 /* after transmission, # of colls */
202:
203: /* transmit control register aliases */
204: #define TCR_OWCSFD 0 /* start after start of frame delimiter */
205: #define TCR_OWCPRE TCR_POWC /* start after first bit of preamble */
206:
207:
208: /*
209: * The interrupt mask register masks the interrupts that
210: * are generated from the interrupt status register.
211: * All reserved bits should be written with 0.
212: */
213: #define IMR_BREN 0x4000 /* bus retry occurred enable */
214: #define IMR_HBLEN 0x2000 /* heartbeat lost enable */
215: #define IMR_LCDEN 0x1000 /* load CAM done interrupt enable */
216: #define IMR_PINTEN 0x0800 /* programmable interrupt enable */
217: #define IMR_PRXEN 0x0400 /* packet received enable */
218: #define IMR_PTXEN 0x0200 /* packet transmitted enable */
219: #define IMR_TXEREN 0x0100 /* transmit error enable */
220: #define IMR_TCEN 0x0080 /* timer complete enable */
221: #define IMR_RDEEN 0x0040 /* receive descriptors exhausted enable */
222: #define IMR_RBEEN 0x0020 /* receive buffers exhausted enable */
223: #define IMR_RBAEEN 0x0010 /* receive buffer area exceeded enable */
224: #define IMR_CRCEN 0x0008 /* CRC tally counter rollover enable */
225: #define IMR_FAEEN 0x0004 /* FAE tally counter rollover enable */
226: #define IMR_MPEN 0x0002 /* MP tally counter rollover enable */
227: #define IMR_RFOEN 0x0001 /* receive FIFO overrun enable */
228:
229:
230: /*
231: * The interrupt status register indicates the source of an interrupt when
232: * the INT pin goes active. The interrupt is acknowledged by writing
233: * the appropriate bit(s) in this register.
234: */
235: #define ISR_ALL 0x7fff /* all interrupts */
236: #define ISR_BR 0x4000 /* bus retry occurred */
237: #define ISR_HBL 0x2000 /* CD heartbeat lost */
238: #define ISR_LCD 0x1000 /* load CAM command has completed */
239: #define ISR_PINT 0x0800 /* programmed interrupt from TXpkt.config */
240: #define ISR_PKTRX 0x0400 /* packet received */
241: #define ISR_TXDN 0x0200 /* no remaining packets to be transmitted */
242: #define ISR_TXER 0x0100 /* packet transmission caused error */
243: #define ISR_TC 0x0080 /* timer complete */
244: #define ISR_RDE 0x0040 /* receive descriptors exhausted */
245: #define ISR_RBE 0x0020 /* receive buffers exhausted */
246: #define ISR_RBAE 0x0010 /* receive buffer area exceeded */
247: #define ISR_CRC 0x0008 /* CRC tally counter rollover */
248: #define ISR_FAE 0x0004 /* FAE tally counter rollover */
249: #define ISR_MP 0x0002 /* MP tally counter rollover */
250: #define ISR_RFO 0x0001 /* receive FIFO overrun */
251:
252: /*
253: * The second data configuration register allows additional user defined
254: * pins to be controlled. These bits are only available if s_dcr.DCR_EXBUS
255: * is set.
256: */
257: #define DCR2_EXPO3 0x8000 /* EXUSR3 output */
258: #define DCR2_EXPO2 0x4000 /* EXUSR2 output */
259: #define DCR2_EXPO1 0x2000 /* EXUSR1 output */
260: #define DCR2_EXPO0 0x1000 /* EXUSR0 output */
261: #define DCR2_PHL 0x0010 /* extend HOLD signal by 1/2 clock */
262: #define DCR2_LRDY 0x0008 /* set latched ready mode */
263: #define DCR2_PCM 0x0004 /* packet compress on match */
264: #define DCR2_PCNM 0x0002 /* packet compress on mismatch */
265: #define DCR2_RJM 0x0001 /* reject on match */
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