Annotation of sys/arch/mac68k/dev/if_mcreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: if_mcreg.h,v 1.2 2004/12/15 06:48:24 martin Exp $ */
! 2: /* NetBSD: if_mcreg.h,v 1.3 2004/03/26 12:15:46 wiz Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1997 David Huang <khym@azeotrope.org>
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. The name of the author may not be used to endorse or promote products
! 14: * derived from this software without specific prior written permission
! 15: *
! 16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 19: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 26: *
! 27: */
! 28:
! 29: /*
! 30: * AMD MACE (Am79C940) register definitions
! 31: */
! 32: #define MACE_RCVFIFO 0 /* Receive FIFO [15-00] (read only) */
! 33: #define MACE_XMTFIFO 1 /* Transmit FIFO [15-00] (write only) */
! 34: #define MACE_XMTFC 2 /* Transmit Frame Control (read/write) */
! 35: #define MACE_XMTFS 3 /* Transmit Frame Status (read only) */
! 36: #define MACE_XMTRC 4 /* Transmit Retry Count (read only) */
! 37: #define MACE_RCVFC 5 /* Receive Frame Control (read/write) */
! 38: #define MACE_RCVFS 6 /* Receive Frame Status (4 bytes) (read only) */
! 39: #define MACE_FIFOFC 7 /* FIFO Frame Count (read only) */
! 40: #define MACE_IR 8 /* Interrupt Register (read only) */
! 41: #define MACE_IMR 9 /* Interrupt Mask Register (read/write) */
! 42: #define MACE_PR 10 /* Poll Register (read only) */
! 43: #define MACE_BIUCC 11 /* BIU Configuration Control (read/write) */
! 44: #define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */
! 45: #define MACE_MACCC 13 /* MAC Configuration Control (read/write) */
! 46: #define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */
! 47: #define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */
! 48: #define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */
! 49: #define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */
! 50: #define MACE_IAC 18 /* Internal Address Configuration (read/write) */
! 51: /* RESERVED 19 Reserved (read/write as 0) */
! 52: #define MACE_LADRF 20 /* Logical Address Filter (8 bytes) (read/write) */
! 53: #define MACE_PADR 21 /* Physical Address (6 bytes) (read/write) */
! 54: /* RESERVED 22 Reserved (read/write as 0) */
! 55: /* RESERVED 23 Reserved (read/write as 0) */
! 56: #define MACE_MPC 24 /* Missed Packet Count (read only) */
! 57: /* RESERVED 25 Reserved (read/write as 0) */
! 58: #define MACE_RNTPC 26 /* Runt Packet Count (read only) */
! 59: #define MACE_RCVCC 27 /* Receive Collision Count (read only) */
! 60: /* RESERVED 28 Reserved (read/write as 0) */
! 61: #define MACE_UTR 29 /* User Test Register (read/write) */
! 62: #define MACE_RTR1 30 /* Reserved Test Register 1 (read/write as 0) */
! 63: #define MACE_RTR2 31 /* Reserved Test Register 2 (read/write as 0) */
! 64:
! 65: #define MACE_NREGS 32
! 66:
! 67: /* 2: Transmit Frame Control (XMTFC) */
! 68: #define DRTRY 0x80 /* Disable Retry */
! 69: #define DXMTFCS 0x08 /* Disable Transmit FCS */
! 70: #define APADXMT 0x01 /* Auto Pad Transmit */
! 71:
! 72: /* 3: Transmit Frame Status (XMTFS) */
! 73: #define XMTSV 0x80 /* Transmit Status Valid */
! 74: #define UFLO 0x40 /* Underflow */
! 75: #define LCOL 0x20 /* Late Collision */
! 76: #define MORE 0x10 /* More than one retry needed */
! 77: #define ONE 0x08 /* Exactly one retry needed */
! 78: #define DEFER 0x04 /* Transmission deferred */
! 79: #define LCAR 0x02 /* Loss of Carrier */
! 80: #define RTRY 0x01 /* Retry Error */
! 81:
! 82: /* 4: Transmit Retry Count (XMTRC) */
! 83: #define EXDEF 0x80 /* Excessive Defer */
! 84: #define XMTRC 0x0f /* Transmit Retry Count */
! 85:
! 86: /* 5: Receive Frame Control (RCVFC) */
! 87: #define LLRCV 0x08 /* Low Latency Receive */
! 88: #define MR 0x04 /* Match/Reject */
! 89: #define ASTRPRCV 0x01 /* Auto Strip Receive */
! 90:
! 91: /* 6: Receive Frame Status (RCVFS) */
! 92: /* 4 byte register; read 4 times to get all of the bytes */
! 93: /* Read 1: RFS0 - Receive Message Byte Count [7-0] (RCVCNT) */
! 94:
! 95: /* Read 2: RFS1 - Receive Status (RCVSTS) */
! 96: #define OFLO 0x80 /* Overflow flag */
! 97: #define CLSN 0x40 /* Collision flag */
! 98: #define FRAM 0x20 /* Framing Error flag */
! 99: #define FCS 0x10 /* FCS Error flag */
! 100: #define RCVCNT 0x0f /* Receive Message Byte Count [11-8] */
! 101:
! 102: /* Read 3: RFS2 - Runt Packet Count (RNTPC) [7-0] */
! 103:
! 104: /* Read 4: RFS3 - Receive Collision Count (RCVCC) [7-0] */
! 105:
! 106: /* 7: FIFO Frame Count (FIFOFC) */
! 107: #define RCVFC 0xf0 /* Receive Frame Count */
! 108: #define XMTFC 0x0f /* Transmit Frame Count */
! 109:
! 110: /* 8: Interrupt Register (IR) */
! 111: #define JAB 0x80 /* Jabber Error */
! 112: #define BABL 0x40 /* Babble Error */
! 113: #define CERR 0x20 /* Collision Error */
! 114: #define RCVCCO 0x10 /* Receive Collision Count Overflow */
! 115: #define RNTPCO 0x08 /* Runt Packet Count Overflow */
! 116: #define MPCO 0x04 /* Missed Packet Count Overflow */
! 117: #define RCVINT 0x02 /* Receive Interrupt */
! 118: #define XMTINT 0x01 /* Transmit Interrupt */
! 119:
! 120: /* 9: Interrut Mask Register (IMR) */
! 121: #define JABM 0x80 /* Jabber Error Mask */
! 122: #define BABLM 0x40 /* Babble Error Mask */
! 123: #define CERRM 0x20 /* Collision Error Mask */
! 124: #define RCVCCOM 0x10 /* Receive Collision Count Overflow Mask */
! 125: #define RNTPCOM 0x08 /* Runt Packet Count Overflow Mask */
! 126: #define MPCOM 0x04 /* Missed Packet Count Overflow Mask */
! 127: #define RCVINTM 0x02 /* Receive Interrupt Mask */
! 128: #define XMTINTM 0x01 /* Transmit Interrupt Mask */
! 129:
! 130: /* 10: Poll Register (PR) */
! 131: #define XMTSV 0x80 /* Transmit Status Valid */
! 132: #define TDTREQ 0x40 /* Transmit Data Transfer Request */
! 133: #define RDTREQ 0x20 /* Receive Data Transfer Request */
! 134:
! 135: /* 11: BIU Configuration Control (BIUCC) */
! 136: #define BSWP 0x40 /* Byte Swap */
! 137: #define XMTSP 0x30 /* Transmit Start Point */
! 138: #define XMTSP_4 0x00 /* 4 bytes */
! 139: #define XMTSP_16 0x10 /* 16 bytes */
! 140: #define XMTSP_64 0x20 /* 64 bytes */
! 141: #define XMTSP_112 0x30 /* 112 bytes */
! 142: #define SWRST 0x01 /* Software Reset */
! 143:
! 144: /* 12: FIFO Configuration Control (FIFOCC) */
! 145: #define XMTFW 0xc0 /* Transmit FIFO Watermark */
! 146: #define XMTFW_8 0x00 /* 8 write cycles */
! 147: #define XMTFW_16 0x40 /* 16 write cycles */
! 148: #define XMTFW_32 0x80 /* 32 write cycles */
! 149: #define RCVFW 0x30 /* Receive FIFO Watermark */
! 150: #define RCVFW_16 0x00 /* 16 bytes */
! 151: #define RCVFW_32 0x10 /* 32 bytes */
! 152: #define RCVFW_64 0x20 /* 64 bytes */
! 153: #define XMTFWU 0x08 /* Transmit FIFO Watermark Update */
! 154: #define RCVFWU 0x04 /* Receive FIFO Watermark Update */
! 155: #define XMTBRST 0x02 /* Transmit Burst */
! 156: #define RCVBRST 0x01 /* Receive Burst */
! 157:
! 158: /* 13: MAC Configuration (MACCC) */
! 159: #define PROM 0x80 /* Promiscuous */
! 160: #define DXMT2PD 0x40 /* Disable Transmit Two Part Deferral */
! 161: #define EMBA 0x20 /* Enable Modified Back-off Algorithm */
! 162: #define DRCVPA 0x08 /* Disable Receive Physical Address */
! 163: #define DRCVBC 0x04 /* Disable Receive Broadcast */
! 164: #define ENXMT 0x02 /* Enable Transmit */
! 165: #define ENRCV 0x01 /* Enable Receive */
! 166:
! 167: /* 14: PLS Configuration Control (PLSCC) */
! 168: #define XMTSEL 0x08 /* Transmit Mode Select */
! 169: #define PORTSEL 0x06 /* Port Select */
! 170: #define PORTSEL_AUI 0x00 /* Select AUI */
! 171: #define PORTSEL_10BT 0x02 /* Select 10BASE-T */
! 172: #define PORTSEL_DAI 0x04 /* Select DAI port */
! 173: #define PORTSEL_GPSI 0x06 /* Select GPSI */
! 174: #define ENPLSIO 0x01 /* Enable PLS I/O */
! 175:
! 176: /* 15: PHY Configuration (PHYCC) */
! 177: #define LNKFL 0x80 /* Link Fail */
! 178: #define DLNKTST 0x40 /* Disable Link Test */
! 179: #define REVPOL 0x20 /* Reversed Polarity */
! 180: #define DAPC 0x10 /* Disable Auto Polarity Correction */
! 181: #define LRT 0x08 /* Low Receive Threshold */
! 182: #define ASEL 0x04 /* Auto Select */
! 183: #define RWAKE 0x02 /* Remote Wake */
! 184: #define AWAKE 0x01 /* Auto Wake */
! 185:
! 186: /* 18: Internal Address Configuration (IAC) */
! 187: #define ADDRCHG 0x80 /* Address Change */
! 188: #define PHYADDR 0x04 /* Physical Address Reset */
! 189: #define LOGADDR 0x02 /* Logical Address Reset */
! 190:
! 191: /* 28: User Test Register (UTR) */
! 192: #define RTRE 0x80 /* Reserved Test Register Enable */
! 193: #define RTRD 0x40 /* Reserved Test Register Disable */
! 194: #define RPA 0x20 /* Run Packet Accept */
! 195: #define FCOLL 0x10 /* Force Collision */
! 196: #define RCVFCSE 0x08 /* Receive FCS Enable */
! 197: #define LOOP 0x06 /* Loopback Control */
! 198: #define LOOP_NONE 0x00 /* No Loopback */
! 199: #define LOOP_EXT 0x02 /* External Loopback */
! 200: #define LOOP_INT 0x04 /* Internal Loopback, excludes MENDEC */
! 201: #define LOOP_INT_MENDEC 0x06 /* Internal Loopback, includes MENDEC */
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