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File: [local] / sys / arch / mac68k / dev / if_aereg.h (download)
Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:07:15 2008 UTC (16 years, 6 months ago) by nbrk
Import of OpenBSD 4.2 release kernel tree with initial code to support Jornada 720/728, StrongARM 1110-based handheld PC. At this point kernel roots on NFS and boots into vfs_mountroot() and traps. What is supported: - glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode (needs some palette tweaks for non black/white/blue colors, i think) - saic, SA11x0 interrupt controller (needs cleanup) - sacom, SA11x0 UART (supported only as boot console for now) - SA11x0 GPIO controller fully supported (but can't handle multiple interrupt handlers on one gpio pin) - sassp, SSP port on SA11x0 that attaches spibus - Jornada microcontroller (jmcu) to control kbd, battery, etc throught the SPI bus (wskbd attaches on jmcu, but not tested) - tod functions seem work - initial code for SA-1111 (chip companion) : this is TODO Next important steps, i think: - gpio and intc on sa1111 - pcmcia support for sa11x0 (and sa1111 help logic) - REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs) - root on wd0! (using already supported PCMCIA-ATA) |
/* $OpenBSD: if_aereg.h,v 1.8 2007/01/22 13:17:45 martin Exp $ */ /* $NetBSD: if_aereg.h,v 1.17 1998/08/12 07:19:09 scottr Exp $ */ /* * National Semiconductor DS8390 NIC register definitions. * * Copyright (C) 1993, David Greenman. This software may be used, modified, * copied, distributed, and sold, in both source and binary form provided that * the above copyright and these terms are retained. Under no circumstances is * the author responsible for the proper functioning of this software, nor does * the author assume any responsibility for damages incurred with its use. */ /* * Memory offsets from slot base PA */ #define GC_RESET_OFFSET 0x000c0000 /* writes here reset NIC */ #define GC_ROM_OFFSET 0x000c0000 /* address prom */ #define GC_DATA_OFFSET 0x000d0000 /* Offset to NIC memory */ #define GC_REG_OFFSET 0x000e0000 /* Offset to NIC registers */ #define DP_ROM_OFFSET 0x000f0000 #define DP_DATA_OFFSET 0x000d0000 /* Offset to SONIC memory */ #define DP_REG_OFFSET 0x000e0000 /* Offset to SONIC registers */ #define AE_ROM_OFFSET 0x000f0000 #define AE_DATA_OFFSET 0x000d0000 /* Offset to NIC memory */ #define AE_REG_OFFSET 0x000e0000 /* Offset to NIC registers */ #define FE_ROM_OFFSET 0x000d0006 /* Determined empirically */ #define KE_ROM_OFFSET 0x000f0007 #define KE_DATA_OFFSET 0x00000000 /* Offset to NIC memory */ #define KE_REG_OFFSET 0x00080003 /* Offset to NIC registers */ #define CT_ROM_OFFSET 0x00030000 /* ROM offset */ #define CT_DATA_OFFSET 0x00000000 /* RAM offset */ #define CT_REG_OFFSET 0x00010000 /* REG offset */ #define AE_REG_SIZE 0x40 /* Size of register space */