Annotation of sys/arch/m88k/include/m8820x.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: m8820x.h,v 1.7 2006/05/06 16:59:26 miod Exp $ */
! 2: /*
! 3: * Copyright (c) 2004, Miodrag Vallat.
! 4: *
! 5: * Redistribution and use in source and binary forms, with or without
! 6: * modification, are permitted provided that the following conditions
! 7: * are met:
! 8: * 1. Redistributions of source code must retain the above copyright
! 9: * notice, this list of conditions and the following disclaimer.
! 10: * 2. Redistributions in binary form must reproduce the above copyright
! 11: * notice, this list of conditions and the following disclaimer in the
! 12: * documentation and/or other materials provided with the distribution.
! 13: *
! 14: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 15: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 16: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 17: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 18: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 19: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 20: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 21: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 22: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 23: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 24: * POSSIBILITY OF SUCH DAMAGE.
! 25: */
! 26: /*
! 27: * Mach Operating System
! 28: * Copyright (c) 1993-1992 Carnegie Mellon University
! 29: * All Rights Reserved.
! 30: *
! 31: * Permission to use, copy, modify and distribute this software and its
! 32: * documentation is hereby granted, provided that both the copyright
! 33: * notice and this permission notice appear in all copies of the
! 34: * software, derivative works or modified versions, and any portions
! 35: * thereof, and that both notices appear in supporting documentation.
! 36: *
! 37: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
! 38: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
! 39: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 40: *
! 41: * Carnegie Mellon requests users of this software to return to
! 42: *
! 43: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
! 44: * School of Computer Science
! 45: * Carnegie Mellon University
! 46: * Pittsburgh PA 15213-3890
! 47: *
! 48: * any improvements or extensions that they make and grant Carnegie Mellon
! 49: * the rights to redistribute these changes.
! 50: */
! 51:
! 52: #ifndef __M88K_M8820X_H__
! 53: #define __M88K_M8820X_H__
! 54:
! 55: /*
! 56: * 8820x CMMU definitions
! 57: */
! 58:
! 59: /* CMMU registers */
! 60: #define CMMU_IDR (0x000 / 4) /* CMMU id register */
! 61: #define CMMU_SCR (0x004 / 4) /* system command register */
! 62: #define CMMU_SSR (0x008 / 4) /* system status register */
! 63: #define CMMU_SAR (0x00c / 4) /* system address register */
! 64: #define CMMU_SCTR (0x104 / 4) /* system control register */
! 65: #define CMMU_PFSR (0x108 / 4) /* P bus fault status register */
! 66: #define CMMU_PFAR (0x10c / 4) /* P bus fault address register */
! 67: #define CMMU_SAPR (0x200 / 4) /* supervisor area pointer register */
! 68: #define CMMU_UAPR (0x204 / 4) /* user area pointer register */
! 69: #define CMMU_BWP0 (0x400 / 4) /* block ATC writer port 0 */
! 70: #define CMMU_BWP1 (0x404 / 4) /* block ATC writer port 1 */
! 71: #define CMMU_BWP2 (0x408 / 4) /* block ATC writer port 2 */
! 72: #define CMMU_BWP3 (0x40c / 4) /* block ATC writer port 3 */
! 73: #define CMMU_BWP4 (0x410 / 4) /* block ATC writer port 4 */
! 74: #define CMMU_BWP5 (0x414 / 4) /* block ATC writer port 5 */
! 75: #define CMMU_BWP6 (0x418 / 4) /* block ATC writer port 6 */
! 76: #define CMMU_BWP7 (0x41c / 4) /* block ATC writer port 7 */
! 77: #define CMMU_BWP(n) (CMMU_BWP0 + (n))
! 78: #define CMMU_CDP0 (0x800 / 4) /* cache data port 0 */
! 79: #define CMMU_CDP1 (0x804 / 4) /* cache data port 1 */
! 80: #define CMMU_CDP2 (0x808 / 4) /* cache data port 2 */
! 81: #define CMMU_CDP3 (0x80c / 4) /* cache data port 3 */
! 82: #define CMMU_CTP0 (0x840 / 4) /* cache tag port 0 */
! 83: #define CMMU_CTP1 (0x844 / 4) /* cache tag port 1 */
! 84: #define CMMU_CTP2 (0x848 / 4) /* cache tag port 2 */
! 85: #define CMMU_CTP3 (0x84c / 4) /* cache tag port 3 */
! 86: #define CMMU_CSSP0 (0x880 / 4) /* cache set status register */
! 87: #define CMMU_CSSP(n) ((0x880 + (n * 0x10)) / 4)
! 88: /* the following only exist on 88204 */
! 89: #define CMMU_CSSP1 (0x890 / 4) /* cache set status register */
! 90: #define CMMU_CSSP2 (0x8a0 / 4) /* cache set status register */
! 91: #define CMMU_CSSP3 (0x8b0 / 4) /* cache set status register */
! 92:
! 93: /* system commands */
! 94: #define CMMU_FLUSH_CACHE_INV_LINE 0x14 /* data cache invalidate */
! 95: #define CMMU_FLUSH_CACHE_INV_PAGE 0x15
! 96: #define CMMU_FLUSH_CACHE_INV_SEGMENT 0x16
! 97: #define CMMU_FLUSH_CACHE_INV_ALL 0x17
! 98: #define CMMU_FLUSH_CACHE_CB_LINE 0x18 /* data cache copyback */
! 99: #define CMMU_FLUSH_CACHE_CB_PAGE 0x19
! 100: #define CMMU_FLUSH_CACHE_CB_SEGMENT 0x1a
! 101: #define CMMU_FLUSH_CACHE_CB_ALL 0x1b
! 102: #define CMMU_FLUSH_CACHE_CBI_LINE 0x1c /* copyback and invalidate */
! 103: #define CMMU_FLUSH_CACHE_CBI_PAGE 0x1d
! 104: #define CMMU_FLUSH_CACHE_CBI_SEGMENT 0x1e
! 105: #define CMMU_FLUSH_CACHE_CBI_ALL 0x1f
! 106: #define CMMU_PROBE_USER 0x20 /* probe user address */
! 107: #define CMMU_PROBE_SUPER 0x24 /* probe supervisor address */
! 108: #define CMMU_FLUSH_USER_LINE 0x30 /* flush PATC */
! 109: #define CMMU_FLUSH_USER_PAGE 0x31
! 110: #define CMMU_FLUSH_USER_SEGMENT 0x32
! 111: #define CMMU_FLUSH_USER_ALL 0x33
! 112: #define CMMU_FLUSH_SUPER_LINE 0x34
! 113: #define CMMU_FLUSH_SUPER_PAGE 0x35
! 114: #define CMMU_FLUSH_SUPER_SEGMENT 0x36
! 115: #define CMMU_FLUSH_SUPER_ALL 0x37
! 116:
! 117: /* system control values */
! 118: #define CMMU_SCTR_PE 0x00008000 /* parity enable */
! 119: #define CMMU_SCTR_SE 0x00004000 /* snoop enable */
! 120: #define CMMU_SCTR_PR 0x00002000 /* priority arbitration */
! 121:
! 122: /* P bus fault status */
! 123: #define CMMU_PFSR_FAULT(pfsr) (((pfsr) >> 16) & 0x07)
! 124: #define CMMU_PFSR_SUCCESS 0 /* no fault */
! 125: #define CMMU_PFSR_BERROR 3 /* bus error */
! 126: #define CMMU_PFSR_SFAULT 4 /* segment fault */
! 127: #define CMMU_PFSR_PFAULT 5 /* page fault */
! 128: #define CMMU_PFSR_SUPER 6 /* supervisor violation */
! 129: #define CMMU_PFSR_WRITE 7 /* writer violation */
! 130:
! 131: /* CSSP values */
! 132: #define CMMU_CSSP_L5 0x20000000
! 133: #define CMMU_CSSP_L4 0x10000000
! 134: #define CMMU_CSSP_L3 0x08000000
! 135: #define CMMU_CSSP_L2 0x04000000
! 136: #define CMMU_CSSP_L1 0x02000000
! 137: #define CMMU_CSSP_L0 0x01000000
! 138: #define CMMU_CSSP_D3 0x00800000
! 139: #define CMMU_CSSP_D2 0x00400000
! 140: #define CMMU_CSSP_D1 0x00200000
! 141: #define CMMU_CSSP_D0 0x00100000
! 142: #define CMMU_CSSP_VV(n,v) (((v) & 0x03) << (12 + 2 * (n)))
! 143: #define CMMU_VV_EXCLUSIVE 0x00
! 144: #define CMMU_VV_MODIFIED 0x01
! 145: #define CMMU_VV_SHARED 0x02
! 146: #define CMMU_VV_INVALID 0x03
! 147:
! 148: /* IDR values */
! 149: #define CMMU_ID(idr) ((idr) >> 24)
! 150: #define CMMU_TYPE(idr) (((idr) >> 21) & 0x07)
! 151: #define CMMU_VERSION(idr) (((idr) >> 16) & 0x1f)
! 152: #define M88200_ID 5
! 153: #define M88204_ID 6
! 154:
! 155: /* SSR values */
! 156: #define CMMU_SSR_CE 0x00008000 /* copyback error */
! 157: #define CMMU_SSR_BE 0x00004000 /* bus error */
! 158: #define CMMU_SSR_SO 0x00000100
! 159: #define CMMU_SSR_M 0x00000010
! 160: #define CMMU_SSR_U 0x00000008
! 161: #define CMMU_SSR_PROT 0x00000004
! 162: #define CMMU_SSR_BH 0x00000002 /* probe BATC hit */
! 163: #define CMMU_SSR_V 0x00000001
! 164:
! 165: /*
! 166: * Cache line information
! 167: */
! 168:
! 169: #define MC88200_CACHE_SHIFT 4
! 170: #define MC88200_CACHE_LINE (1 << MC88200_CACHE_SHIFT)
! 171:
! 172: /*
! 173: * Hardwired BATC information
! 174: */
! 175:
! 176: #define BATC8 0xfff7ffb5
! 177: #define BATC9 0xfffffff5
! 178:
! 179: #define BATC8_VA 0xfff00000
! 180: #define BATC9_VA 0xfff80000
! 181:
! 182: #define NBSG (1 << (PDT_BITS + PG_BITS)) /* segment size */
! 183:
! 184: #ifndef _LOCORE
! 185:
! 186: /*
! 187: * CMMU kernel information
! 188: */
! 189: struct m8820x_cmmu {
! 190: volatile u_int32_t *cmmu_regs; /* CMMU "base" area */
! 191: #ifdef M88200_HAS_SPLIT_ADDRESS
! 192: vaddr_t cmmu_addr; /* address range */
! 193: vaddr_t cmmu_addr_mask; /* address mask */
! 194: #endif
! 195: };
! 196:
! 197: #define INST_CMMU 0x00 /* even number */
! 198: #define DATA_CMMU 0x01 /* odd number */
! 199: #define CMMU_MODE(num) ((num) & 1)
! 200:
! 201: #define MAX_CMMUS 8 /* maximum cmmus on the board */
! 202: extern struct m8820x_cmmu m8820x_cmmu[MAX_CMMUS];
! 203: extern u_int cmmu_shift;
! 204: extern u_int max_cmmus;
! 205:
! 206: void m8820x_setup_board_config(void);
! 207: cpuid_t m8820x_cpu_number(void);
! 208:
! 209: #endif /* _LOCORE */
! 210: #endif /* __M88K_M8820X_H__ */
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