Annotation of sys/arch/m68k/m68k/db_disasm.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: db_disasm.h,v 1.4 2002/03/14 01:26:34 millert Exp $ */
! 2: /* $NetBSD: db_disasm.h,v 1.4 1996/04/01 01:38:12 briggs Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1994 Christian E. Hopps
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: * 3. All advertising materials mentioning features or use of this software
! 17: * must display the following acknowledgement:
! 18: * This product includes software developed by Christian E. Hopps.
! 19: * 4. The name of the author may not be used to endorse or promote products
! 20: * derived from this software without specific prior written permission
! 21: *
! 22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 32: */
! 33:
! 34: #define ENCB(b7,b6,b5,b4,b3,b2,b1,b0) \
! 35: ((b7 << 7) | (b6 << 6) | (b5 << 5) | (b4 << 4) | \
! 36: (b3 << 3) | (b2 << 2) | (b1 << 1) | (b0))
! 37:
! 38:
! 39: #define ENCW(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
! 40: ((ENCB(b15,b14,b13,b12,b11,b10,b9,b8) << 8) |\
! 41: ENCB(b7,b6,b5,b4,b3,b2,b1,b0))
! 42:
! 43: /*
! 44: * Group Bit-manip (0000)
! 45: */
! 46: #define ANDITOCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1)
! 47: #define ANDIROSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1)
! 48: #define EORITOCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1)
! 49: #define EORITOSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1)
! 50: #define ORITOCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1)
! 51: #define ORITOSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1)
! 52: #define ANDITOCCR_INST ENCW(0,0,0,0, 0,0,1,0, 0,0,1,1, 1,1,0,0)
! 53: #define ANDIROSR_INST ENCW(0,0,0,0, 0,0,1,0, 0,1,1,1, 1,1,0,0)
! 54: #define EORITOCCR_INST ENCW(0,0,0,0, 1,0,1,0, 0,0,1,1, 1,1,0,0)
! 55: #define EORITOSR_INST ENCW(0,0,0,0, 1,0,1,0, 0,1,1,1, 1,1,0,0)
! 56: #define ORITOCCR_INST ENCW(0,0,0,0, 0,0,0,0, 0,0,1,1, 1,1,0,0)
! 57: #define ORITOSR_INST ENCW(0,0,0,0, 0,0,0,0, 0,1,1,1, 1,1,0,0)
! 58:
! 59: /*
! 60: * RTM: this is what gas *and* my amiga assembler spit out, however
! 61: * my moto manual disagrees, another 030 manual I have also has
! 62: * something different from all of the above!
! 63: *
! 64: * BTW there may be a consipircy, as many may recognize
! 65: * from the acronym associated with this opcode's name. *grin*
! 66: */
! 67: #define RTM_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 0,0,0,0)
! 68: #define RTM_INST ENCW(0,0,0,0, 0,1,1,0, 1,1,0,0, 0,0,0,0)
! 69:
! 70: /* Note: bit eight being 1 here allows these to be check before all else */
! 71:
! 72: /* Note: for movp bits 5-3, specify a mode An, which all the other
! 73: * bit 8 set commands do not, so have check first. */
! 74: #define MOVEP_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,1,1, 1,0,0,0)
! 75: #define MOVEP_INST ENCW(0,0,0,0, 0,0,0,1, 0,0,0,0, 1,0,0,0)
! 76:
! 77: #define BCHGD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 78: #define BCLRD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 79: #define BSETD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 80: #define BTSTD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 81: #define BCHGD_INST ENCW(0,0,0,0, 0,0,0,1, 0,1,0,0, 0,0,0,0)
! 82: #define BCLRD_INST ENCW(0,0,0,0, 0,0,0,1, 1,0,0,0, 0,0,0,0)
! 83: #define BSETD_INST ENCW(0,0,0,0, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 84: #define BTSTD_INST ENCW(0,0,0,0, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 85:
! 86: #define BCHGS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 87: #define BCLRS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 88: #define BSETS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 89: #define BTSTS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 90: #define BCHGS_INST ENCW(0,0,0,0, 1,0,0,0, 0,1,0,0, 0,0,0,0)
! 91: #define BCLRS_INST ENCW(0,0,0,0, 1,0,0,0, 1,0,0,0, 0,0,0,0)
! 92: #define BSETS_INST ENCW(0,0,0,0, 1,0,0,0, 1,1,0,0, 0,0,0,0)
! 93: #define BTSTS_INST ENCW(0,0,0,0, 1,0,0,0, 0,0,0,0, 0,0,0,0)
! 94:
! 95: #define CAS2_MASK ENCW(1,1,1,1, 1,1,0,1, 1,1,1,1, 1,1,1,1)
! 96: #define CAS2_INST ENCW(0,0,0,0, 1,1,0,0, 1,1,1,1, 1,1,0,0)
! 97:
! 98: #define CAS_MASK ENCW(1,1,1,1, 1,0,0,1, 1,1,0,0, 0,0,0,0)
! 99: #define CHK2_MASK ENCW(1,1,1,1, 1,0,0,1, 1,1,0,0, 0,0,0,0)
! 100: #define CMP2_MASK ENCW(1,1,1,1, 1,0,0,1, 1,1,0,0, 0,0,0,0)
! 101: #define CAS_INST ENCW(0,0,0,0, 1,0,0,0, 1,1,0,0, 0,0,0,0)
! 102: #define CHK2_INST ENCW(0,0,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 103: #define CMP2_INST ENCW(0,0,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 104:
! 105: /* close ties with Bxxx but bit eight here is 0 and there 1 */
! 106: /* also above (cas,chk2,cmp2) bits 7-6 here are size and never 11 */
! 107: #define ADDI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 108: #define ANDI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 109: #define CMPI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 110: #define EORI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 111: #define MOVES_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 112: #define ORI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 113: #define SUBI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 114: #define ADDI_INST ENCW(0,0,0,0, 0,1,1,0, 0,0,0,0, 0,0,0,0)
! 115: #define ANDI_INST ENCW(0,0,0,0, 0,0,1,0, 0,0,0,0, 0,0,0,0)
! 116: #define CMPI_INST ENCW(0,0,0,0, 1,1,0,0, 0,0,0,0, 0,0,0,0)
! 117: #define EORI_INST ENCW(0,0,0,0, 1,0,1,0, 0,0,0,0, 0,0,0,0)
! 118: #define MOVES_INST ENCW(0,0,0,0, 1,1,1,0, 0,0,0,0, 0,0,0,0)
! 119: #define ORI_INST ENCW(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 120: #define SUBI_INST ENCW(0,0,0,0, 0,1,0,0, 0,0,0,0, 0,0,0,0)
! 121:
! 122: /*
! 123: * Group misc. (0100)
! 124: */
! 125: #define BGND_MASK 0xffff
! 126: #define ILLEGAL_MASK 0xffff
! 127: #define MOVEFRC_MASK 0xffff
! 128: #define MOVETOC_MASK 0xffff
! 129: #define NOP_MASK 0xffff
! 130: #define RESET_MASK 0xffff
! 131: #define RTD_MASk 0xffff
! 132: #define RTE_MASK 0xffff
! 133: #define RTR_MASK 0xffff
! 134: #define RTS_MASK 0xffff
! 135: #define STOP_MASK 0xffff
! 136: #define TRAPV_MASK 0xffff
! 137: #define BGND_INST ENCW(0,1,0,0, 1,0,1,0, 1,1,1,1, 1,0,1,0)
! 138: #define ILLEGAL_INST ENCW(0,1,0,0, 1,0,1,0, 1,1,1,1, 1,1,0,0)
! 139: #define MOVEFRC_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 1,0,1,0)
! 140: #define MOVETOC_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 1,0,1,1)
! 141: #define NOP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,0,0,1)
! 142: #define RESET_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,0,0,0)
! 143: #define RTD_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,1,0,0)
! 144: #define RTE_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,0,1,1)
! 145: #define RTR_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,1,1,1)
! 146: #define RTS_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,1,0,1)
! 147: #define STOP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,0,1,0)
! 148: #define TRAPV_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,1,1,0)
! 149: #define SWAP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 150: #define SWAP_INST ENCW(0,1,0,0, 1,0,0,0, 0,1,0,0, 0,0,0,0)
! 151:
! 152: #define BKPT_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 153: #define EXTBW_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 154: #define EXTWL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 155: #define EXTBL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 156: #define LINKW_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 157: #define LINKL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 158: #define MOVEFRUSP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 159: #define MOVETOUSP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 160: #define UNLK_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0)
! 161: #undef BKPT_INST
! 162: #define BKPT_INST ENCW(0,1,0,0, 1,0,0,0, 0,1,0,0, 1,0,0,0)
! 163: #define EXTBW_INST ENCW(0,1,0,0, 1,0,0,0, 1,0,0,0, 0,0,0,0)
! 164: #define EXTWL_INST ENCW(0,1,0,0, 1,0,0,0, 1,1,0,0, 0,0,0,0)
! 165: #define EXTBL_INST ENCW(0,1,0,0, 1,0,0,1, 1,1,0,0, 0,0,0,0)
! 166: #define LINKW_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,0,1, 0,0,0,0)
! 167: #define LINKL_INST ENCW(0,1,0,0, 1,0,0,0, 0,0,0,0, 1,0,0,0)
! 168: #define MOVETOUSP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,0, 0,0,0,0)
! 169: #define MOVEFRUSP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,0, 1,0,0,0)
! 170: #define UNLK_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,0,1, 1,0,0,0)
! 171:
! 172: #define TRAP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 0,0,0,0)
! 173: #define TRAP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,0,0, 0,0,0,0)
! 174:
! 175: #define DIVSL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 176: #define DIVUL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 177: #define JMP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 178: #define JSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 179: #define MOVEFRCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 180: #define MOVETOCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 181: #define MOVEFRSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 182: #define MOVETOSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 183: #define MULSL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 184: #define MULUL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 185: #define NBCD_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 186: #define PEA_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 187: #define TAS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 188: #define DIVSL_INST ENCW(0,1,0,0, 1,1,0,0, 0,1,0,0, 0,0,0,0)
! 189: #define DIVUL_INST DIVSL_INST
! 190: #define JMP_INST ENCW(0,1,0,0, 1,1,1,0, 1,1,0,0, 0,0,0,0)
! 191: #define JSR_INST ENCW(0,1,0,0, 1,1,1,0, 1,0,0,0, 0,0,0,0)
! 192: #define MOVEFRCCR_INST ENCW(0,1,0,0, 0,0,1,0, 1,1,0,0, 0,0,0,0)
! 193: #define MOVETOCCR_INST ENCW(0,1,0,0, 0,1,0,0, 1,1,0,0, 0,0,0,0)
! 194: #define MOVEFRSR_INST ENCW(0,1,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 195: #define MOVETOSR_INST ENCW(0,1,0,0, 0,1,1,0, 1,1,0,0, 0,0,0,0)
! 196: #define MULSL_INST ENCW(0,1,0,0, 1,1,0,0, 0,0,0,0, 0,0,0,0)
! 197: #define MULUL_INST MULSL_INST
! 198: #define NBCD_INST ENCW(0,1,0,0, 1,0,0,0, 0,0,0,0, 0,0,0,0)
! 199: #define PEA_INST ENCW(0,1,0,0, 1,0,0,0, 0,1,0,0, 0,0,0,0)
! 200: #define TAS_INST ENCW(0,1,0,0, 1,0,1,0, 1,1,0,0, 0,0,0,0)
! 201:
! 202: #define MOVEM_MASK ENCW(1,1,1,1, 1,0,1,1, 1,0,0,0, 0,0,0,0)
! 203: #define MOVEM_INST ENCW(0,1,0,0, 1,0,0,0, 1,0,0,0, 0,0,0,0)
! 204:
! 205: #define CLR_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 206: #define NEG_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 207: #define NEGX_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 208: #define NOT_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 209: #define TST_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 210: #define CLR_INST ENCW(0,1,0,0, 0,0,1,0, 0,0,0,0, 0,0,0,0)
! 211: #define NEG_INST ENCW(0,1,0,0, 0,1,0,0, 0,0,0,0, 0,0,0,0)
! 212: #define NEGX_INST ENCW(0,1,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 213: #define NOT_INST ENCW(0,1,0,0, 0,1,1,0, 0,0,0,0, 0,0,0,0)
! 214: /* Note: very similatr to MOVEM but bit 9 differentiates. */
! 215: #define TST_INST ENCW(0,1,0,0, 1,0,1,0, 0,0,0,0, 0,0,0,0)
! 216:
! 217: #define LEA_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 218: #define LEA_INST ENCW(0,1,0,0, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 219:
! 220: #define CHK_MASK ENCW(1,1,1,1, 0,0,0,1, 0,1,0,0, 0,0,0,0)
! 221: #define CHK_INST ENCW(0,1,0,0, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 222:
! 223: /*
! 224: * Group bitfield/Shift/Rotate. (1110)
! 225: */
! 226: #define BFCHG_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 227: #define BFCLR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 228: #define BFEXTS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 229: #define BFEXTU_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 230: #define BFFFO_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 231: #define BFINS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 232: #define BFSET_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 233: #define BFTST_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 234:
! 235: #define BFCHG_INST ENCW(1,1,1,0, 1,0,1,0, 1,1,0,0, 0,0,0,0)
! 236: #define BFCLR_INST ENCW(1,1,1,0, 1,1,0,0, 1,1,0,0, 0,0,0,0)
! 237: #define BFEXTS_INST ENCW(1,1,1,0, 1,0,1,1, 1,1,0,0, 0,0,0,0)
! 238: #define BFEXTU_INST ENCW(1,1,1,0, 1,0,0,1, 1,1,0,0, 0,0,0,0)
! 239: #define BFFFO_INST ENCW(1,1,1,0, 1,1,0,1, 1,1,0,0, 0,0,0,0)
! 240: #define BFINS_INST ENCW(1,1,1,0, 1,1,1,1, 1,1,0,0, 0,0,0,0)
! 241: #define BFSET_INST ENCW(1,1,1,0, 1,1,1,0, 1,1,0,0, 0,0,0,0)
! 242: #define BFTST_INST ENCW(1,1,1,0, 1,0,0,0, 1,1,0,0, 0,0,0,0)
! 243:
! 244: #define AS_TYPE 0x0
! 245: #define LS_TYPE 0x1
! 246: #define RO_TYPE 0x3
! 247: #define ROX_TYPE 0x2
! 248:
! 249: /*
! 250: * Group DBcc/TRAPcc/ADDQ/SUBQ (0101)
! 251: */
! 252: #define DBcc_MASK ENCW(1,1,1,1, 0,0,0,0, 1,1,1,1, 1,0,0,0)
! 253: #define TRAPcc_MASK ENCW(1,1,1,1, 0,0,0,0, 1,1,1,1, 1,0,0,0)
! 254: #define Scc_MASK ENCW(1,1,1,1, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 255: #define ADDQ_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 256: #define SUBQ_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 257: #define DBcc_INST ENCW(0,1,0,1, 0,0,0,0, 1,1,0,0, 1,0,0,0)
! 258: #define TRAPcc_INST ENCW(0,1,0,1, 0,0,0,0, 1,1,1,1, 1,0,0,0)
! 259: #define Scc_INST ENCW(0,1,0,1, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 260: #define ADDQ_INST ENCW(0,1,0,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 261: #define SUBQ_INST ENCW(0,1,0,1, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 262:
! 263: /*
! 264: * Group ADD/ADDX (1101)
! 265: */
! 266: #define ADDX_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,1,1, 0,0,0,0)
! 267: #define ADDX_INST ENCW(1,1,0,1, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 268: #define ADD_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 269: #define ADD_INST ENCW(1,1,0,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 270:
! 271: /*
! 272: * Group SUB/SUBX (1001)
! 273: */
! 274: #define SUBX_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,1,1, 0,0,0,0)
! 275: #define SUBX_INST ENCW(1,0,0,1, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 276: #define SUB_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 277: #define SUB_INST ENCW(1,0,0,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 278:
! 279: /*
! 280: * Group CMP/CMPA/EOR (1011)
! 281: */
! 282: #define CMPA_MASK ENCW(1,1,1,1, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 283: #define CMPA_INST ENCW(1,0,1,1, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 284:
! 285: #define CMP_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 286: #define CMP_INST ENCW(1,0,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 287:
! 288: #define EOR_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 289: #define EOR_INST ENCW(1,0,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 290:
! 291: /*
! 292: * Group branch. (0110)
! 293: */
! 294: #define BRA_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 295: #define BSR_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0)
! 296: #define Bcc_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 297: #define BRA_INST ENCW(0,1,1,0, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 298: #define BSR_INST ENCW(0,1,1,0, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 299: #define Bcc_INST ENCW(0,1,1,0, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 300:
! 301:
! 302: /*
! 303: * Group SBCD/DIVx/OR (1000)
! 304: */
! 305:
! 306: #define UNPKA_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0)
! 307: #define UNPKD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0)
! 308: #define UNPKA_INST ENCW(1,0,0,0, 0,0,0,1, 1,0,0,0, 1,0,0,0)
! 309: #define UNPKD_INST ENCW(1,0,0,0, 0,0,0,1, 1,0,0,0, 0,0,0,0)
! 310: #define SBCDA_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0)
! 311: #define SBCDD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0)
! 312: #define SBCDA_INST ENCW(1,0,0,0, 0,0,0,1, 0,0,0,0, 1,1,1,1)
! 313: #define SBCDD_INST ENCW(1,0,0,0, 0,0,0,1, 0,0,0,0, 0,1,1,1)
! 314:
! 315: #define DIVSW_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 316: #define DIVUW_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 317: #define DIVSW_INST ENCW(1,0,0,0, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 318: #define DIVUW_INST ENCW(1,0,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 319:
! 320: #define OR_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 321: #define OR_INST ENCW(1,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 322:
! 323: /*
! 324: * Group AND/MUL/ABCD/EXG (1100)
! 325: */
! 326: #define ABCDA_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0)
! 327: #define ABCDD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0)
! 328: #define ABCDA_INST ENCW(1,1,0,0, 0,0,0,1, 0,0,0,0, 1,0,0,0)
! 329: #define ABCDD_INST ENCW(1,1,0,0, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 330:
! 331: #define MULSW_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 332: #define MULUW_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 333: #define MULSW_INST ENCW(1,1,0,0, 0,0,0,1, 1,1,0,0, 0,0,0,0)
! 334: #define MULUW_INST ENCW(1,1,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0)
! 335:
! 336: #define EXG_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,1,1, 0,0,0,0)
! 337: #define EXG_INST ENCW(1,1,0,0, 0,0,0,1, 0,0,0,0, 0,0,0,0)
! 338:
! 339: #define AND_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 340: #define AND_INST ENCW(1,1,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0)
! 341:
! 342: #define ENCFT(b5,b4,b3,b2,b1,b0) ENCB(0,0,b5,b4,b3,b2,b1,b0)
! 343:
! 344: #define FABS ENCFT(0,1,1,0,0,0)
! 345: #define FACOS ENCFT(0,1,1,1,0,0)
! 346: #define FADD ENCFT(1,0,0,0,1,0)
! 347: #define FASIN ENCFT(0,0,1,1,0,0)
! 348: #define FATAN ENCFT(0,0,1,0,1,0)
! 349: #define FATANH ENCFT(0,0,1,1,0,1)
! 350: #define FCMP ENCFT(1,1,1,0,0,0)
! 351: #define FCOS ENCFT(0,1,1,1,0,1)
! 352: #define FCOSH ENCFT(0,1,1,0,0,1)
! 353: #define FDIV ENCFT(1,0,0,0,0,0)
! 354: #define FETOX ENCFT(0,1,0,0,0,0)
! 355: #define FGETEXP ENCFT(0,1,1,1,1,0)
! 356: #define FGETMAN ENCFT(0,1,1,1,1,1)
! 357: #define FINT ENCFT(0,0,0,0,0,1)
! 358: #define FINTRZ ENCFT(0,0,0,0,1,1)
! 359: #define FLOG10 ENCFT(0,1,0,1,0,1)
! 360: #define FLOG2 ENCFT(0,1,0,1,1,0)
! 361: #define FLOGN ENCFT(0,1,0,1,0,0)
! 362: #define FLOGNP1 ENCFT(0,0,0,1,1,0)
! 363: #define FMOD ENCFT(1,0,0,0,0,1)
! 364: #define FMOVE ENCFT(0,0,0,0,0,0)
! 365: #define FMUL ENCFT(1,0,0,0,1,1)
! 366: #define FNEG ENCFT(0,1,1,0,1,0)
! 367: #define FREM ENCFT(1,0,0,1,0,1)
! 368: #undef FSCALE
! 369: #define FSCALE ENCFT(1,0,0,1,1,0)
! 370: #define FSGLDIV ENCFT(1,0,0,1,0,0)
! 371: #define FSGLMUL ENCFT(1,0,0,1,1,1)
! 372: #define FSIN ENCFT(0,0,1,1,1,0)
! 373: #define FSINH ENCFT(0,0,0,0,1,0)
! 374: #define FSQRT ENCFT(0,0,0,1,0,0)
! 375: #define FSUB ENCFT(1,0,1,0,0,0)
! 376: #define FTAN ENCFT(0,0,1,1,1,1)
! 377: #define FTANH ENCFT(0,0,1,0,0,1)
! 378: #define FTENTOX ENCFT(0,1,0,0,1,0)
! 379: #define FTST ENCFT(1,1,1,0,1,0)
! 380: #define FTWOTOX ENCFT(0,1,0,0,0,1)
! 381:
! 382: enum getmod_flag { GETMOD_BEFORE = -1, GETMOD_AFTER = -2 };
! 383:
! 384: enum opcode_flags {
! 385: CPU_000 = 0x1, CPU_010 = 0x2, CPU_020 = 0x4, CPU_030 = 0x8,
! 386: CPU_040 = 0x10, FPU_881 = 0x40, FPU_882 = 0x80, FPU_040 = 0x100,
! 387: MMU_851 = 0x400, MMU_030 = 0x800, MMU_040 = 0x1000,
! 388:
! 389: CPU_ANY = CPU_000 | CPU_010 | CPU_020 | CPU_030 | CPU_040,
! 390: FPU_ANY = FPU_881 | FPU_882 | FPU_040,
! 391: MMU_ANY = MMU_851 | MMU_030 | MMU_040,
! 392: CPU_020UP = CPU_020 | CPU_030 | CPU_040,
! 393: };
! 394:
! 395: enum mod_types {
! 396: DR_DIR = 0,
! 397: AR_DIR, AR_IND, AR_INC, AR_DEC,
! 398: AR_DIS, AR_IDX, MOD_SPECIAL
! 399: };
! 400:
! 401: enum sizes { SIZE_BYTE = sizeof(char), SIZE_WORD = sizeof(short),
! 402: SIZE_LONG = sizeof(long), SIZE_SINGLE = 5, SIZE_QUAD = 6,
! 403: SIZE_DOUBLE = SIZE_QUAD, SIZE_EXTENDED = 7, SIZE_PACKED = 8 };
! 404:
! 405: struct dis_buffer {
! 406: short *val; /* pointer to memory. */
! 407: char *dasm; /* actual dasm. */
! 408: char *casm; /* current position in dasm. */
! 409: char *info; /* extra info. */
! 410: char *cinfo; /* current position in info. */
! 411: int used; /* length used. */
! 412: int mit; /* use mit sytanx. */
! 413: };
! 414: typedef struct dis_buffer dis_buffer_t;
! 415:
! 416: #define ISBITSET(val,b) ((val) & (1 << (b)))
! 417: #define BITFIELD_MASK(sb,eb) (((1 << ((sb) + 1))-1) & (~((1 << (eb))-1)))
! 418: #define BITFIELD(val,sb,eb) ((BITFIELD_MASK(sb,eb) & (val)) >> (eb))
! 419: #define OPCODE_MAP(x) (BITFIELD(x,15,12))
! 420: #ifdef __STDC__
! 421: #define IS_INST(inst,val) ((inst ## _MASK & (val)) == inst ## _INST)
! 422: #else
! 423: #define IS_INST(inst,val) ((inst/**/_MASK & (val)) == inst/**/_INST)
! 424: #endif
! 425: #define PRINT_FPREG(dbuf, reg) addstr(dbuf, fpregs[reg])
! 426: #define PRINT_DREG(dbuf, reg) addstr(dbuf, dregs[reg])
! 427: #define PRINT_AREG(dbuf, reg) addstr(dbuf, aregs[reg])
! 428:
! 429: db_addr_t db_disasm(db_addr_t loc, boolean_t moto_syntax);
! 430: void get_modregstr_moto(dis_buffer_t *dbuf, int bit, int mod, int sz, int dd);
! 431: void get_modregstr_mit(dis_buffer_t *dbuf, int bit, int mod, int sz, int dd);
! 432: u_long get_areg_val(int reg);
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