Annotation of sys/arch/m68k/include/pte_motorola.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pte_motorola.h,v 1.5 2005/09/25 22:19:57 miod Exp $ */
2:
3: /*
4: * Copyright (c) 1988 University of Utah.
5: * Copyright (c) 1982, 1986, 1990, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This code is derived from software contributed to Berkeley by
9: * the Systems Programming Group of the University of Utah Computer
10: * Science Department.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * from: Utah $Hdr: pte.h 1.13 92/01/20$
37: *
38: * @(#)pte.h 8.1 (Berkeley) 6/10/93
39: */
40:
41: #ifndef _PTE_MOTOROLA_H_
42: #define _PTE_MOTOROLA_H_
43:
44: /*
45: * m68k hardware with motorola MMU segment/page table entries
46: */
47:
48: typedef int st_entry_t; /* segment table entry */
49: typedef int pt_entry_t; /* Mach page table entry */
50:
51: #define PT_ENTRY_NULL ((pt_entry_t *) 0)
52: #define ST_ENTRY_NULL ((st_entry_t *) 0)
53:
54: #define SG_V 0x00000002 /* segment is valid */
55: #define SG_NV 0x00000000
56: #define SG_PROT 0x00000004 /* access protection mask */
57: #define SG_RO 0x00000004
58: #define SG_RW 0x00000000
59: #define SG_U 0x00000008 /* modified bit (68040) */
60: #define SG_FRAME 0xfffff000
61: #define SG_IMASK 0xffc00000
62: #define SG_ISHIFT 22
63: #define SG_PMASK 0x003ff000
64: #define SG_PSHIFT 12
65:
66: /* 68040 additions */
67: #define SG4_MASK1 0xfe000000
68: #define SG4_SHIFT1 25
69: #define SG4_MASK2 0x01fc0000
70: #define SG4_SHIFT2 18
71: #define SG4_MASK3 0x0003f000
72: #define SG4_SHIFT3 12
73: #define SG4_ADDR1 0xfffffe00
74: #define SG4_ADDR2 0xffffff00
75: #define SG4_LEV1SIZE 128
76: #define SG4_LEV2SIZE 128
77: #define SG4_LEV3SIZE 64
78:
79: #define PG_V 0x00000001
80: #define PG_NV 0x00000000
81: #define PG_PROT 0x00000004
82: #define PG_U 0x00000008
83: #define PG_M 0x00000010
84: #define PG_W 0x00000100
85: #define PG_RO 0x00000004
86: #define PG_RW 0x00000000
87: #define PG_FRAME 0xfffff000
88: #define PG_CI 0x00000040
89: #define PG_SHIFT 12
90: #define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT)
91:
92: /* 68040 additions */
93: #define PG_CMASK 0x00000060 /* cache mode mask */
94: #define PG_CWT 0x00000000 /* writethrough caching */
95: #define PG_CCB 0x00000020 /* copyback caching */
96: #define PG_CIS 0x00000040 /* cache inhibited serialized */
97: #define PG_CIN 0x00000060 /* cache inhibited nonserialized */
98: #define PG_SO 0x00000080 /* supervisor only */
99:
100: #define M68K_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t))
101: /* user process segment table size */
102: #define M68K_MAX_PTSIZE 0x400000 /* max size of UPT */
103: #define M68K_MAX_KPTSIZE 0x100000 /* max memory to allocate to KPT */
104: #define M68K_PTBASE 0x10000000 /* UPT map base address */
105: #define M68K_PTMAXSIZE 0x70000000 /* UPT map maximum size */
106:
107: /*
108: * Kernel virtual address to page table entry and to physical address.
109: */
110: #define kvtopte(va) \
111: (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT])
112:
113: #endif /* !_PTE_MOTOROLA_H_ */
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