Annotation of sys/arch/m68k/fpsp/x_ovfl.sa, Revision 1.1.1.1
1.1 nbrk 1: * $OpenBSD: x_ovfl.sa,v 1.3 2001/09/20 17:02:30 mpech Exp $
2: * $NetBSD: x_ovfl.sa,v 1.2 1994/10/26 07:50:26 cgd Exp $
3:
4: * MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
5: * M68000 Hi-Performance Microprocessor Division
6: * M68040 Software Package
7: *
8: * M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc.
9: * All rights reserved.
10: *
11: * THE SOFTWARE is provided on an "AS IS" basis and without warranty.
12: * To the maximum extent permitted by applicable law,
13: * MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
14: * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
15: * PARTICULAR PURPOSE and any warranty against infringement with
16: * regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
17: * and any accompanying written materials.
18: *
19: * To the maximum extent permitted by applicable law,
20: * IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
21: * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS
22: * PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
23: * OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
24: * SOFTWARE. Motorola assumes no responsibility for the maintenance
25: * and support of the SOFTWARE.
26: *
27: * You are hereby granted a copyright license to use, modify, and
28: * distribute the SOFTWARE so long as this entire notice is retained
29: * without alteration in any modified and/or redistributed versions,
30: * and that such modified versions are clearly identified as such.
31: * No licenses are granted by implication, estoppel or otherwise
32: * under any patents or trademarks of Motorola, Inc.
33:
34: *
35: * x_ovfl.sa 3.5 7/1/91
36: *
37: * fpsp_ovfl --- FPSP handler for overflow exception
38: *
39: * Overflow occurs when a floating-point intermediate result is
40: * too large to be represented in a floating-point data register,
41: * or when storing to memory, the contents of a floating-point
42: * data register are too large to be represented in the
43: * destination format.
44: *
45: * Trap disabled results
46: *
47: * If the instruction is move_out, then garbage is stored in the
48: * destination. If the instruction is not move_out, then the
49: * destination is not affected. For 68881 compatibility, the
50: * following values should be stored at the destination, based
51: * on the current rounding mode:
52: *
53: * RN Infinity with the sign of the intermediate result.
54: * RZ Largest magnitude number, with the sign of the
55: * intermediate result.
56: * RM For pos overflow, the largest pos number. For neg overflow,
57: * -infinity
58: * RP For pos overflow, +infinity. For neg overflow, the largest
59: * neg number
60: *
61: * Trap enabled results
62: * All trap disabled code applies. In addition the exceptional
63: * operand needs to be made available to the users exception handler
64: * with a bias of $6000 subtracted from the exponent.
65: *
66:
67: X_OVFL IDNT 2,1 Motorola 040 Floating Point Software Package
68:
69: section 8
70:
71: include fpsp.h
72:
73: xref ovf_r_x2
74: xref ovf_r_x3
75: xref store
76: xref real_ovfl
77: xref real_inex
78: xref fpsp_done
79: xref g_opcls
80: xref b1238_fix
81:
82: xdef fpsp_ovfl
83: fpsp_ovfl:
84: link a6,#-LOCAL_SIZE
85: fsave -(a7)
86: movem.l d0-d1/a0-a1,USER_DA(a6)
87: fmovem.x fp0-fp3,USER_FP0(a6)
88: fmovem.l fpcr/fpsr/fpiar,USER_FPCR(a6)
89:
90: *
91: * The 040 doesn't set the AINEX bit in the FPSR, the following
92: * line temporarily rectifies this error.
93: *
94: bset.b #ainex_bit,FPSR_AEXCEPT(a6)
95: *
96: bsr.l ovf_adj ;denormalize, round & store interm op
97: *
98: * if overflow traps not enabled check for inexact exception
99: *
100: btst.b #ovfl_bit,FPCR_ENABLE(a6)
101: beq.b ck_inex
102: *
103: btst.b #E3,E_BYTE(a6)
104: beq.b no_e3_1
105: bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no
106: bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
107: bsr.l b1238_fix
108: move.l USER_FPSR(a6),FPSR_SHADOW(a6)
109: or.l #sx_mask,E_BYTE(a6)
110: no_e3_1:
111: movem.l USER_DA(a6),d0-d1/a0-a1
112: fmovem.x USER_FP0(a6),fp0-fp3
113: fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
114: frestore (a7)+
115: unlk a6
116: bra.l real_ovfl
117: *
118: * It is possible to have either inex2 or inex1 exceptions with the
119: * ovfl. If the inex enable bit is set in the FPCR, and either
120: * inex2 or inex1 occurred, we must clean up and branch to the
121: * real inex handler.
122: *
123: ck_inex:
124: * move.b FPCR_ENABLE(a6),d0
125: * and.b FPSR_EXCEPT(a6),d0
126: * andi.b #$3,d0
127: btst.b #inex2_bit,FPCR_ENABLE(a6)
128: beq.b ovfl_exit
129: *
130: * Inexact enabled and reported, and we must take an inexact exception.
131: *
132: take_inex:
133: btst.b #E3,E_BYTE(a6)
134: beq.b no_e3_2
135: bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no
136: bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
137: bsr.l b1238_fix
138: move.l USER_FPSR(a6),FPSR_SHADOW(a6)
139: or.l #sx_mask,E_BYTE(a6)
140: no_e3_2:
141: move.b #INEX_VEC,EXC_VEC+1(a6)
142: movem.l USER_DA(a6),d0-d1/a0-a1
143: fmovem.x USER_FP0(a6),fp0-fp3
144: fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
145: frestore (a7)+
146: unlk a6
147: bra.l real_inex
148:
149: ovfl_exit:
150: bclr.b #E3,E_BYTE(a6) ;test and clear E3 bit
151: beq.b e1_set
152: *
153: * Clear dirty bit on dest resister in the frame before branching
154: * to b1238_fix.
155: *
156: bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no
157: bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
158: bsr.l b1238_fix ;test for bug1238 case
159:
160: move.l USER_FPSR(a6),FPSR_SHADOW(a6)
161: or.l #sx_mask,E_BYTE(a6)
162: movem.l USER_DA(a6),d0-d1/a0-a1
163: fmovem.x USER_FP0(a6),fp0-fp3
164: fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
165: frestore (a7)+
166: unlk a6
167: bra.l fpsp_done
168: e1_set:
169: movem.l USER_DA(a6),d0-d1/a0-a1
170: fmovem.x USER_FP0(a6),fp0-fp3
171: fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
172: unlk a6
173: bra.l fpsp_done
174:
175: *
176: * ovf_adj
177: *
178: ovf_adj:
179: *
180: * Have a0 point to the correct operand.
181: *
182: btst.b #E3,E_BYTE(a6) ;test E3 bit
183: beq.b ovf_e1
184:
185: lea WBTEMP(a6),a0
186: bra.b ovf_com
187: ovf_e1:
188: lea ETEMP(a6),a0
189:
190: ovf_com:
191: bclr.b #sign_bit,LOCAL_EX(a0)
192: sne LOCAL_SGN(a0)
193:
194: bsr.l g_opcls ;returns opclass in d0
195: cmpi.w #3,d0 ;check for opclass3
196: bne.b not_opc011
197:
198: *
199: * FPSR_CC is saved and restored because ovf_r_x3 affects it. The
200: * CCs are defined to be 'not affected' for the opclass3 instruction.
201: *
202: move.b FPSR_CC(a6),L_SCR1(a6)
203: bsr.l ovf_r_x3 ;returns a0 pointing to result
204: move.b L_SCR1(a6),FPSR_CC(a6)
205: bra.l store ;stores to memory or register
206:
207: not_opc011:
208: bsr.l ovf_r_x2 ;returns a0 pointing to result
209: bra.l store ;stores to memory or register
210:
211: end
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