Annotation of sys/arch/m68k/fpsp/fpsp.h, Revision 1.1.1.1
1.1 nbrk 1: * $OpenBSD: fpsp.h,v 1.2 1996/05/29 21:05:28 niklas Exp $
2: * $NetBSD: fpsp.h,v 1.2 1994/10/26 07:49:04 cgd Exp $
3:
4: * MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
5: * M68000 Hi-Performance Microprocessor Division
6: * M68040 Software Package
7: *
8: * M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc.
9: * All rights reserved.
10: *
11: * THE SOFTWARE is provided on an "AS IS" basis and without warranty.
12: * To the maximum extent permitted by applicable law,
13: * MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
14: * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
15: * PARTICULAR PURPOSE and any warranty against infringement with
16: * regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
17: * and any accompanying written materials.
18: *
19: * To the maximum extent permitted by applicable law,
20: * IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
21: * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS
22: * PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
23: * OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
24: * SOFTWARE. Motorola assumes no responsibility for the maintenance
25: * and support of the SOFTWARE.
26: *
27: * You are hereby granted a copyright license to use, modify, and
28: * distribute the SOFTWARE so long as this entire notice is retained
29: * without alteration in any modified and/or redistributed versions,
30: * and that such modified versions are clearly identified as such.
31: * No licenses are granted by implication, estoppel or otherwise
32: * under any patents or trademarks of Motorola, Inc.
33:
34: *
35: * fpsp.h 3.3 3.3
36: *
37:
38: * fpsp.h --- stack frame offsets during FPSP exception handling
39: *
40: * These equates are used to access the exception frame, the fsave
41: * frame and any local variables needed by the FPSP package.
42: *
43: * All FPSP handlers begin by executing:
44: *
45: * link a6,#-LOCAL_SIZE
46: * fsave -(a7)
47: * movem.l d0-d1/a0-a1,USER_DA(a6)
48: * fmovem.x fp0-fp3,USER_FP0(a6)
49: * fmove.l fpsr/fpcr/fpiar,USER_FPSR(a6)
50: *
51: * After initialization, the stack looks like this:
52: *
53: * A7 ---> +-------------------------------+
54: * | |
55: * | FPU fsave area |
56: * | |
57: * +-------------------------------+
58: * | |
59: * | FPSP Local Variables |
60: * | including |
61: * | saved registers |
62: * | |
63: * +-------------------------------+
64: * A6 ---> | Saved A6 |
65: * +-------------------------------+
66: * | |
67: * | Exception Frame |
68: * | |
69: * | |
70: *
71: * Positive offsets from A6 refer to the exception frame. Negative
72: * offsets refer to the Local Variable area and the fsave area.
73: * The fsave frame is also accessible 'from the top' via A7.
74: *
75: * On exit, the handlers execute:
76: *
77: * movem.l USER_DA(a6),d0-d1/a0-a1
78: * fmovem.x USER_FP0(a6),fp0-fp3
79: * fmove.l USER_FPSR(a6),fpsr/fpcr/fpiar
80: * frestore (a7)+
81: * unlk a6
82: *
83: * and then either 'bra fpsp_done' if the exception was completely
84: * handled by the package, or 'bra real_xxxx' which is an external
85: * label to a routine that will process a real exception of the
86: * type that was generated. Some handlers may omit the 'frestore'
87: * if the FPU state after the exception is idle.
88: *
89: * Sometimes the exception handler will transform the fsave area
90: * because it needs to report an exception back to the user. This
91: * can happen if the package is entered for an unimplemented float
92: * instruction that generates (say) an underflow. Alternatively,
93: * a second fsave frame can be pushed onto the stack and the
94: * handler exit code will reload the new frame and discard the old.
95: *
96: * The registers d0, d1, a0, a1 and fp0-fp3 are always saved and
97: * restored from the 'local variable' area and can be used as
98: * temporaries. If a routine needs to change any
99: * of these registers, it should modify the saved copy and let
100: * the handler exit code restore the value.
101: *
102: *----------------------------------------------------------------------
103: *
104: * Local Variables on the stack
105: *
106: LOCAL_SIZE equ 192 ;bytes needed for local variables
107: LV equ -LOCAL_SIZE ;convenient base value
108: *
109: USER_DA equ LV+0 ;save space for D0-D1,A0-A1
110: USER_D0 equ LV+0 ;saved user D0
111: USER_D1 equ LV+4 ;saved user D1
112: USER_A0 equ LV+8 ;saved user A0
113: USER_A1 equ LV+12 ;saved user A1
114: USER_FP0 equ LV+16 ;saved user FP0
115: USER_FP1 equ LV+28 ;saved user FP1
116: USER_FP2 equ LV+40 ;saved user FP2
117: USER_FP3 equ LV+52 ;saved user FP3
118: USER_FPCR equ LV+64 ;saved user FPCR
119: FPCR_ENABLE equ USER_FPCR+2 ; FPCR exception enable
120: FPCR_MODE equ USER_FPCR+3 ; FPCR rounding mode control
121: USER_FPSR equ LV+68 ;saved user FPSR
122: FPSR_CC equ USER_FPSR+0 ; FPSR condition code
123: FPSR_QBYTE equ USER_FPSR+1 ; FPSR quotient
124: FPSR_EXCEPT equ USER_FPSR+2 ; FPSR exception
125: FPSR_AEXCEPT equ USER_FPSR+3 ; FPSR accrued exception
126: USER_FPIAR equ LV+72 ;saved user FPIAR
127: FP_SCR1 equ LV+76 ;room for a temporary float value
128: FP_SCR2 equ LV+92 ;room for a temporary float value
129: L_SCR1 equ LV+108 ;room for a temporary long value
130: L_SCR2 equ LV+112 ;room for a temporary long value
131: STORE_FLG equ LV+116
132: BINDEC_FLG equ LV+117 ;used in bindec
133: DNRM_FLG equ LV+118 ;used in res_func
134: RES_FLG equ LV+119 ;used in res_func
135: DY_MO_FLG equ LV+120 ;dyadic/monadic flag
136: UFLG_TMP equ LV+121 ;temporary for uflag errata
137: CU_ONLY equ LV+122 ;cu-only flag
138: VER_TMP equ LV+123 ;temp holding for version number
139: L_SCR3 equ LV+124 ;room for a temporary long value
140: FP_SCR3 equ LV+128 ;room for a temporary float value
141: FP_SCR4 equ LV+144 ;room for a temporary float value
142: FP_SCR5 equ LV+160 ;room for a temporary float value
143: FP_SCR6 equ LV+176
144: *
145: *NEXT equ LV+192 ;need to increase LOCAL_SIZE
146: *
147: *--------------------------------------------------------------------------
148: *
149: * fsave offsets and bit definitions
150: *
151: * Offsets are defined from the end of an fsave because the last 10
152: * words of a busy frame are the same as the unimplemented frame.
153: *
154: CU_SAVEPC equ LV-92 ;micro-pc for CU (1 byte)
155: FPR_DIRTY_BITS equ LV-91 ;fpr dirty bits
156: *
157: WBTEMP equ LV-76 ;write back temp (12 bytes)
158: WBTEMP_EX equ WBTEMP ;wbtemp sign and exponent (2 bytes)
159: WBTEMP_HI equ WBTEMP+4 ;wbtemp mantissa [63:32] (4 bytes)
160: WBTEMP_LO equ WBTEMP+8 ;wbtemp mantissa [31:00] (4 bytes)
161: *
162: WBTEMP_SGN equ WBTEMP+2 ;used to store sign
163: *
164: FPSR_SHADOW equ LV-64 ;fpsr shadow reg
165: *
166: FPIARCU equ LV-60 ;Instr. addr. reg. for CU (4 bytes)
167: *
168: CMDREG2B equ LV-52 ;cmd reg for machine 2
169: CMDREG3B equ LV-48 ;cmd reg for E3 exceptions (2 bytes)
170: *
171: NMNEXC equ LV-44 ;NMNEXC (unsup,snan bits only)
172: nmn_unsup_bit equ 1
173: nmn_snan_bit equ 0
174: *
175: NMCEXC equ LV-43 ;NMNEXC & NMCEXC
176: nmn_operr_bit equ 7
177: nmn_ovfl_bit equ 6
178: nmn_unfl_bit equ 5
179: nmc_unsup_bit equ 4
180: nmc_snan_bit equ 3
181: nmc_operr_bit equ 2
182: nmc_ovfl_bit equ 1
183: nmc_unfl_bit equ 0
184: *
185: STAG equ LV-40 ;source tag (1 byte)
186: WBTEMP_GRS equ LV-40 ;alias wbtemp guard, round, sticky
187: guard_bit equ 1 ;guard bit is bit number 1
188: round_bit equ 0 ;round bit is bit number 0
189: stag_mask equ $E0 ;upper 3 bits are source tag type
190: denorm_bit equ 7 ;bit determins if denorm or unnorm
191: etemp15_bit equ 4 ;etemp exponent bit #15
192: wbtemp66_bit equ 2 ;wbtemp mantissa bit #66
193: wbtemp1_bit equ 1 ;wbtemp mantissa bit #1
194: wbtemp0_bit equ 0 ;wbtemp mantissa bit #0
195: *
196: STICKY equ LV-39 ;holds sticky bit
197: sticky_bit equ 7
198: *
199: CMDREG1B equ LV-36 ;cmd reg for E1 exceptions (2 bytes)
200: kfact_bit equ 12 ;distinguishes static/dynamic k-factor
201: * ;on packed move out's. NOTE: this
202: * ;equate only works when CMDREG1B is in
203: * ;a register.
204: *
205: CMDWORD equ LV-35 ;command word in cmd1b
206: direction_bit equ 5 ;bit 0 in opclass
207: size_bit2 equ 12 ;bit 2 in size field
208: *
209: DTAG equ LV-32 ;dest tag (1 byte)
210: dtag_mask equ $E0 ;upper 3 bits are dest type tag
211: fptemp15_bit equ 4 ;fptemp exponent bit #15
212: *
213: WB_BYTE equ LV-31 ;holds WBTE15 bit (1 byte)
214: wbtemp15_bit equ 4 ;wbtemp exponent bit #15
215: *
216: E_BYTE equ LV-28 ;holds E1 and E3 bits (1 byte)
217: E1 equ 2 ;which bit is E1 flag
218: E3 equ 1 ;which bit is E3 flag
219: SFLAG equ 0 ;which bit is S flag
220: *
221: T_BYTE equ LV-27 ;holds T and U bits (1 byte)
222: XFLAG equ 7 ;which bit is X flag
223: UFLAG equ 5 ;which bit is U flag
224: TFLAG equ 4 ;which bit is T flag
225: *
226: FPTEMP equ LV-24 ;fptemp (12 bytes)
227: FPTEMP_EX equ FPTEMP ;fptemp sign and exponent (2 bytes)
228: FPTEMP_HI equ FPTEMP+4 ;fptemp mantissa [63:32] (4 bytes)
229: FPTEMP_LO equ FPTEMP+8 ;fptemp mantissa [31:00] (4 bytes)
230: *
231: FPTEMP_SGN equ FPTEMP+2 ;used to store sign
232: *
233: ETEMP equ LV-12 ;etemp (12 bytes)
234: ETEMP_EX equ ETEMP ;etemp sign and exponent (2 bytes)
235: ETEMP_HI equ ETEMP+4 ;etemp mantissa [63:32] (4 bytes)
236: ETEMP_LO equ ETEMP+8 ;etemp mantissa [31:00] (4 bytes)
237: *
238: ETEMP_SGN equ ETEMP+2 ;used to store sign
239: *
240: EXC_SR equ 4 ;exception frame status register
241: EXC_PC equ 6 ;exception frame program counter
242: EXC_VEC equ 10 ;exception frame vector (format+vector#)
243: EXC_EA equ 12 ;exception frame effective address
244: *
245: *--------------------------------------------------------------------------
246: *
247: * FPSR/FPCR bits
248: *
249: neg_bit equ 3 negative result
250: z_bit equ 2 zero result
251: inf_bit equ 1 infinity result
252: nan_bit equ 0 not-a-number result
253: *
254: q_sn_bit equ 7 sign bit of quotient byte
255: *
256: bsun_bit equ 7 branch on unordered
257: snan_bit equ 6 signalling nan
258: operr_bit equ 5 operand error
259: ovfl_bit equ 4 overflow
260: unfl_bit equ 3 underflow
261: dz_bit equ 2 divide by zero
262: inex2_bit equ 1 inexact result 2
263: inex1_bit equ 0 inexact result 1
264: *
265: aiop_bit equ 7 accrued illegal operation
266: aovfl_bit equ 6 accrued overflow
267: aunfl_bit equ 5 accrued underflow
268: adz_bit equ 4 accrued divide by zero
269: ainex_bit equ 3 accrued inexact
270: *
271: * FPSR individual bit masks
272: *
273: neg_mask equ $08000000
274: z_mask equ $04000000
275: inf_mask equ $02000000
276: nan_mask equ $01000000
277: *
278: bsun_mask equ $00008000
279: snan_mask equ $00004000
280: operr_mask equ $00002000
281: ovfl_mask equ $00001000
282: unfl_mask equ $00000800
283: dz_mask equ $00000400
284: inex2_mask equ $00000200
285: inex1_mask equ $00000100
286: *
287: aiop_mask equ $00000080 accrued illegal operation
288: aovfl_mask equ $00000040 accrued overflow
289: aunfl_mask equ $00000020 accrued underflow
290: adz_mask equ $00000010 accrued divide by zero
291: ainex_mask equ $00000008 accrued inexact
292: *
293: * FPSR combinations used in the FPSP
294: *
295: dzinf_mask equ inf_mask+dz_mask+adz_mask
296: opnan_mask equ nan_mask+operr_mask+aiop_mask
297: nzi_mask equ $01ffffff clears N, Z, and I
298: unfinx_mask equ unfl_mask+inex2_mask+aunfl_mask+ainex_mask
299: unf2inx_mask equ unfl_mask+inex2_mask+ainex_mask
300: ovfinx_mask equ ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
301: inx1a_mask equ inex1_mask+ainex_mask
302: inx2a_mask equ inex2_mask+ainex_mask
303: snaniop_mask equ nan_mask+snan_mask+aiop_mask
304: naniop_mask equ nan_mask+aiop_mask
305: neginf_mask equ neg_mask+inf_mask
306: infaiop_mask equ inf_mask+aiop_mask
307: negz_mask equ neg_mask+z_mask
308: opaop_mask equ operr_mask+aiop_mask
309: unfl_inx_mask equ unfl_mask+aunfl_mask+ainex_mask
310: ovfl_inx_mask equ ovfl_mask+aovfl_mask+ainex_mask
311: *
312: *--------------------------------------------------------------------------
313: *
314: * FPCR rounding modes
315: *
316: x_mode equ $00 round to extended
317: s_mode equ $40 round to single
318: d_mode equ $80 round to double
319: *
320: rn_mode equ $00 round nearest
321: rz_mode equ $10 round to zero
322: rm_mode equ $20 round to minus infinity
323: rp_mode equ $30 round to plus infinity
324: *
325: *--------------------------------------------------------------------------
326: *
327: * Miscellaneous equates
328: *
329: signan_bit equ 6 signalling nan bit in mantissa
330: sign_bit equ 7
331: *
332: rnd_stky_bit equ 29 round/sticky bit of mantissa
333: * this can only be used if in a data register
334: sx_mask equ $01800000 set s and x bits in word $48
335: *
336: LOCAL_EX equ 0
337: LOCAL_SGN equ 2
338: LOCAL_HI equ 4
339: LOCAL_LO equ 8
340: LOCAL_GRS equ 12 valid ONLY for FP_SCR1, FP_SCR2
341: *
342: *
343: norm_tag equ $00 tag bits in {7:5} position
344: zero_tag equ $20
345: inf_tag equ $40
346: nan_tag equ $60
347: dnrm_tag equ $80
348: *
349: * fsave sizes and formats
350: *
351: VER_4 equ $40 fpsp compatible version numbers
352: * are in the $40s {$40-$4f}
353: VER_40 equ $40 original version number
354: VER_41 equ $41 revision version number
355: *
356: BUSY_SIZE equ 100 size of busy frame
357: BUSY_FRAME equ LV-BUSY_SIZE start of busy frame
358: *
359: UNIMP_40_SIZE equ 44 size of orig unimp frame
360: UNIMP_41_SIZE equ 52 size of rev unimp frame
361: *
362: IDLE_SIZE equ 4 size of idle frame
363: IDLE_FRAME equ LV-IDLE_SIZE start of idle frame
364: *
365: * exception vectors
366: *
367: TRACE_VEC equ $2024 trace trap
368: FLINE_VEC equ $002C 'real' F-line
369: UNIMP_VEC equ $202C unimplemented
370: INEX_VEC equ $00C4
371: *
372: dbl_thresh equ $3C01
373: sgl_thresh equ $3F81
374: *
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