Annotation of sys/arch/m68k/fpsp/FPSP.sa, Revision 1.1.1.1
1.1 nbrk 1: * $OpenBSD: FPSP.sa,v 1.2 1996/05/29 21:05:20 niklas Exp $
2: * $NetBSD: FPSP.sa,v 1.2 1994/10/26 07:48:33 cgd Exp $
3:
4: * MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
5: * M68000 Hi-Performance Microprocessor Division
6: * M68040 Software Package
7: *
8: * M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc.
9: * All rights reserved.
10: *
11: * THE SOFTWARE is provided on an "AS IS" basis and without warranty.
12: * To the maximum extent permitted by applicable law,
13: * MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
14: * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
15: * PARTICULAR PURPOSE and any warranty against infringement with
16: * regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
17: * and any accompanying written materials.
18: *
19: * To the maximum extent permitted by applicable law,
20: * IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
21: * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS
22: * PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
23: * OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
24: * SOFTWARE. Motorola assumes no responsibility for the maintenance
25: * and support of the SOFTWARE.
26: *
27: * You are hereby granted a copyright license to use, modify, and
28: * distribute the SOFTWARE so long as this entire notice is retained
29: * without alteration in any modified and/or redistributed versions,
30: * and that such modified versions are clearly identified as such.
31: * No licenses are granted by implication, estoppel or otherwise
32: * under any patents or trademarks of Motorola, Inc.
33:
34: *
35: * FPSP.sa 3.1 12/10/90
36: *
37: * Init file for testing FPSP software package.
38: *
39: * Takes over the exception vectors that the FPSP handles.
40: *
41:
42: FPSP IDNT 2,1 Motorola 040 Floating Point Software Package
43:
44: CODE_ST equ $10000 ;address of test code start
45:
46: FLINE_VEC equ $2c
47: BSUN_VEC equ $c0
48: INEX2_VEC equ $c4
49: DZ_VEC equ $c8
50: UNFL_VEC equ $cc
51: OPERR_VEC equ $d0
52: OVFL_VEC equ $d4
53: SNAN_VEC equ $d8
54: UNSUP_VEC equ $dc
55:
56: xref fline,unsupp
57: xref bsun,inex,dz,unfl
58: xref operr,ovfl,snan
59:
60: section 7
61:
62: * Load vector table with addresses of FPSP routines and
63: * branch to CODE_ST, start address of test code.
64:
65: xdef start
66: start:
67: movec.l VBR,a0
68: move.l #fline,FLINE_VEC(a0)
69: move.l #bsun,BSUN_VEC(a0)
70: move.l #inex,INEX2_VEC(a0)
71: move.l #dz,DZ_VEC(a0)
72: move.l #unfl,UNFL_VEC(a0)
73: move.l #operr,OPERR_VEC(a0)
74: move.l #ovfl,OVFL_VEC(a0)
75: move.l #snan,SNAN_VEC(a0)
76: move.l #unsupp,UNSUP_VEC(a0)
77:
78: jmp CODE_ST
79:
80: end
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