Annotation of sys/arch/m68k/fpe/fpu_subr.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: fpu_subr.c,v 1.5 2006/06/11 20:43:28 miod Exp $ */
2: /* $NetBSD: fpu_subr.c,v 1.6 2003/08/07 16:28:12 agc Exp $ */
3:
4: /*
5: * Copyright (c) 1992, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This software was developed by the Computer Systems Engineering group
9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10: * contributed to Berkeley.
11: *
12: * All advertising materials mentioning features or use of this software
13: * must display the following acknowledgement:
14: * This product includes software developed by the University of
15: * California, Lawrence Berkeley Laboratory.
16: *
17: * Redistribution and use in source and binary forms, with or without
18: * modification, are permitted provided that the following conditions
19: * are met:
20: * 1. Redistributions of source code must retain the above copyright
21: * notice, this list of conditions and the following disclaimer.
22: * 2. Redistributions in binary form must reproduce the above copyright
23: * notice, this list of conditions and the following disclaimer in the
24: * documentation and/or other materials provided with the distribution.
25: * 3. Neither the name of the University nor the names of its contributors
26: * may be used to endorse or promote products derived from this software
27: * without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39: * SUCH DAMAGE.
40: *
41: * @(#)fpu_subr.c 8.1 (Berkeley) 6/11/93
42: */
43:
44: /*
45: * FPU subroutines.
46: */
47:
48: #include <sys/types.h>
49: #include <sys/systm.h>
50:
51: #include <machine/reg.h>
52:
53: #include <m68k/fpe/fpu_emulate.h>
54: #include <m68k/fpe/fpu_arith.h>
55:
56: /*
57: * Shift the given number right rsh bits. Any bits that `fall off' will get
58: * shoved into the sticky field; we return the resulting sticky. Note that
59: * shifting NaNs is legal (this will never shift all bits out); a NaN's
60: * sticky field is ignored anyway.
61: */
62: int
63: fpu_shr(struct fpn *fp, int rsh)
64: {
65: u_int m0, m1, m2, s;
66: int lsh;
67:
68: #ifdef DIAGNOSTIC
69: if (rsh < 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp)))
70: panic("fpu_rightshift 1");
71: #endif
72:
73: m0 = fp->fp_mant[0];
74: m1 = fp->fp_mant[1];
75: m2 = fp->fp_mant[2];
76:
77: /* If shifting all the bits out, take a shortcut. */
78: if (rsh >= FP_NMANT) {
79: #ifdef DIAGNOSTIC
80: if ((m0 | m1 | m2) == 0)
81: panic("fpu_rightshift 2");
82: #endif
83: fp->fp_mant[0] = 0;
84: fp->fp_mant[1] = 0;
85: fp->fp_mant[2] = 0;
86: #ifdef notdef
87: if ((m0 | m1 | m2) == 0)
88: fp->fp_class = FPC_ZERO;
89: else
90: #endif
91: fp->fp_sticky = 1;
92: return (1);
93: }
94:
95: /* Squish out full words. */
96: s = fp->fp_sticky;
97: if (rsh >= 32 * 2) {
98: s |= m2 | m1;
99: m2 = m0, m1 = 0, m0 = 0;
100: } else if (rsh >= 32) {
101: s |= m2;
102: m2 = m1, m1 = m0, m0 = 0;
103: }
104:
105: /* Handle any remaining partial word. */
106: if ((rsh &= 31) != 0) {
107: lsh = 32 - rsh;
108: s |= m2 << lsh;
109: m2 = (m2 >> rsh) | (m1 << lsh);
110: m1 = (m1 >> rsh) | (m0 << lsh);
111: m0 >>= rsh;
112: }
113: fp->fp_mant[0] = m0;
114: fp->fp_mant[1] = m1;
115: fp->fp_mant[2] = m2;
116: fp->fp_sticky = s;
117: return (s);
118: }
119:
120: /*
121: * Force a number to be normal, i.e., make its fraction have all zero
122: * bits before FP_1, then FP_1, then all 1 bits. This is used for denorms
123: * and (sometimes) for intermediate results.
124: *
125: * Internally, this may use a `supernormal' -- a number whose fp_mant
126: * is greater than or equal to 2.0 -- so as a side effect you can hand it
127: * a supernormal and it will fix it (provided fp->fp_mant[2] == 0).
128: */
129: void
130: fpu_norm(struct fpn *fp)
131: {
132: u_int m0, m1, m2, sup, nrm;
133: int lsh, rsh, exp;
134:
135: exp = fp->fp_exp;
136: m0 = fp->fp_mant[0];
137: m1 = fp->fp_mant[1];
138: m2 = fp->fp_mant[2];
139:
140: /* Handle severe subnormals with 32-bit moves. */
141: if (m0 == 0) {
142: if (m1) {
143: m0 = m1;
144: m1 = m2;
145: m2 = 0;
146: exp -= 32;
147: } else if (m2) {
148: m0 = m2;
149: m1 = 0;
150: m2 = 0;
151: exp -= 2 * 32;
152: } else {
153: fp->fp_class = FPC_ZERO;
154: return;
155: }
156: }
157:
158: /* Now fix any supernormal or remaining subnormal. */
159: nrm = FP_1;
160: sup = nrm << 1;
161: if (m0 >= sup) {
162: /*
163: * We have a supernormal number. We need to shift it right.
164: * We may assume m2==0.
165: */
166: __asm __volatile("bfffo %1{#0:#32},%0" : "=d"(rsh) : "g"(m0));
167: rsh = 31 - rsh - FP_LG;
168: exp += rsh;
169: lsh = 32 - rsh;
170: m2 = m1 << lsh;
171: m1 = (m1 >> rsh) | (m0 << lsh);
172: m0 = (m0 >> rsh);
173: } else if (m0 < nrm) {
174: /*
175: * We have a regular denorm (a subnormal number), and need
176: * to shift it left.
177: */
178: __asm __volatile("bfffo %1{#0:#32},%0" : "=d"(lsh) : "g"(m0));
179: lsh = FP_LG - 31 + lsh;
180: exp -= lsh;
181: rsh = 32 - lsh;
182: m0 = (m0 << lsh) | (m1 >> rsh);
183: m1 = (m1 << lsh) | (m2 >> rsh);
184: m2 <<= lsh;
185: }
186:
187: fp->fp_exp = exp;
188: fp->fp_mant[0] = m0;
189: fp->fp_mant[1] = m1;
190: fp->fp_mant[2] = m2;
191: }
192:
193: /*
194: * Concoct a `fresh' Quiet NaN per Appendix N.
195: * As a side effect, we set OPERR for the current exceptions.
196: */
197: struct fpn *
198: fpu_newnan(struct fpemu *fe)
199: {
200: struct fpn *fp;
201:
202: fe->fe_fpsr |= FPSR_OPERR;
203: fp = &fe->fe_f3;
204: fp->fp_class = FPC_QNAN;
205: fp->fp_sign = 0;
206: fp->fp_mant[0] = FP_1 - 1;
207: fp->fp_mant[1] = fp->fp_mant[2] = ~0;
208: return (fp);
209: }
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