Annotation of sys/arch/m68k/fpe/fpu_fscale.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: fpu_fscale.c,v 1.8 2006/06/11 20:43:28 miod Exp $ */
2: /* $NetBSD: fpu_fscale.c,v 1.11 2003/07/15 02:43:10 lukem Exp $ */
3:
4: /*
5: * Copyright (c) 1995 Ken Nakata
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. The name of the author may not be used to endorse or promote products
17: * derived from this software without specific prior written permission.
18: * 4. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed by Gordon Ross
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32: */
33:
34: /*
35: * FSCALE - separated from the other type0 arithmetic instructions
36: * for performance reason; maybe unnecessary, but FSCALE assumes
37: * the source operand be an integer. It performs type conversion
38: * only if the source operand is *not* an integer.
39: */
40:
41: #include <sys/types.h>
42: #include <sys/signal.h>
43: #include <sys/systm.h>
44: #include <machine/frame.h>
45:
46: #include <m68k/fpe/fpu_emulate.h>
47:
48: int
49: fpu_emul_fscale(struct fpemu *fe, struct instruction *insn, int *typ)
50: {
51: struct frame *frame;
52: u_int *fpregs;
53: int word1, sig;
54: int regnum, format;
55: int scale, sign, exp;
56: u_int m0, m1;
57: u_int buf[3], fpsr;
58: #if DEBUG_FPE
59: int flags;
60: char regname;
61: #endif
62:
63: scale = sig = 0;
64: frame = fe->fe_frame;
65: fpregs = &(fe->fe_fpframe->fpf_regs[0]);
66: /* clear all exceptions and conditions */
67: fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB;
68: #if DEBUG_FPE
69: printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr);
70: #endif
71:
72: word1 = insn->is_word1;
73: format = (word1 >> 10) & 7;
74: regnum = (word1 >> 7) & 7;
75:
76: fe->fe_fpcr &= FPCR_ROUND;
77: fe->fe_fpcr |= FPCR_ZERO;
78:
79: /* get the source operand */
80: if ((word1 & 0x4000) == 0) {
81: #if DEBUG_FPE
82: printf("fpu_emul_fscale: FP%d op FP%d => FP%d\n",
83: format, regnum, regnum);
84: /* the operand is an FP reg */
85: printf("fpu_emul_scale: src opr FP%d=%08x%08x%08x\n",
86: format, fpregs[format*3], fpregs[format*3+1],
87: fpregs[format*3+2]);
88: #endif
89: fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]);
90: fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf);
91: scale = buf[0];
92: } else {
93: /* the operand is in memory */
94: if (format == FTYPE_DBL) {
95: insn->is_datasize = 8;
96: } else if (format == FTYPE_SNG || format == FTYPE_LNG) {
97: insn->is_datasize = 4;
98: } else if (format == FTYPE_WRD) {
99: insn->is_datasize = 2;
100: } else if (format == FTYPE_BYT) {
101: insn->is_datasize = 1;
102: } else if (format == FTYPE_EXT) {
103: insn->is_datasize = 12;
104: } else {
105: /* invalid or unsupported operand format */
106: *typ = ILL_ILLOPN;
107: sig = SIGILL;
108: return sig;
109: }
110:
111: /* Get effective address. (modreg=opcode&077) */
112: sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode, typ);
113: if (sig) {
114: #if DEBUG_FPE
115: printf("fpu_emul_fscale: error in decode_ea\n");
116: #endif
117: return sig;
118: }
119:
120: #if DEBUG_FPE
121: printf("fpu_emul_fscale: addr mode = ");
122: flags = insn->is_ea.ea_flags;
123: regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd';
124:
125: if (flags & EA_DIRECT) {
126: printf("%c%d\n", regname, insn->is_ea.ea_regnum & 7);
127: } else if (flags & EA_PREDECR) {
128: printf("%c%d@-\n", regname, insn->is_ea.ea_regnum & 7);
129: } else if (flags & EA_POSTINCR) {
130: printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7);
131: } else if (flags & EA_OFFSET) {
132: printf("%c%d@(%d)\n", regname, insn->is_ea.ea_regnum & 7,
133: insn->is_ea.ea_offset);
134: } else if (flags & EA_INDEXED) {
135: printf("%c%d@(...)\n", regname, insn->is_ea.ea_regnum & 7);
136: } else if (flags & EA_ABS) {
137: printf("0x%08x\n", insn->is_ea.ea_absaddr);
138: } else if (flags & EA_PC_REL) {
139: printf("pc@(%d)\n", insn->is_ea.ea_offset);
140: } else if (flags & EA_IMMED) {
141: printf("#0x%08x%08x%08x\n",
142: insn->is_ea.ea_immed[0], insn->is_ea.ea_immed[1],
143: insn->is_ea.ea_immed[2]);
144: } else {
145: printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7);
146: }
147: #endif
148: fpu_load_ea(frame, insn, &insn->is_ea, (char *)buf, typ);
149:
150: #if DEBUG_FPE
151: printf("fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n",
152: buf[0], buf[1], buf[2], insn->is_datasize);
153: #endif
154: if (format == FTYPE_LNG) {
155: /* nothing */
156: scale = buf[0];
157: } else if (format == FTYPE_WRD) {
158: /* sign-extend */
159: scale = buf[0] & 0xffff;
160: if (scale & 0x8000) {
161: scale |= 0xffff0000;
162: }
163: } else if (format == FTYPE_BYT) {
164: /* sign-extend */
165: scale = buf[0] & 0xff;
166: if (scale & 0x80) {
167: scale |= 0xffffff00;
168: }
169: } else if (format == FTYPE_DBL || format == FTYPE_SNG ||
170: format == FTYPE_EXT) {
171: fpu_explode(fe, &fe->fe_f2, format, buf);
172: fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf);
173: scale = buf[0];
174: }
175: /* make it look like we've got an FP oprand */
176: fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM;
177: }
178:
179: /* assume there's no exception */
180: sig = 0;
181:
182: /* it's barbaric but we're going to operate directly on
183: * the dst operand's bit pattern */
184: sign = fpregs[regnum * 3] & 0x80000000;
185: exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16;
186: m0 = fpregs[regnum * 3 + 1];
187: m1 = fpregs[regnum * 3 + 2];
188:
189: switch (fe->fe_f2.fp_class) {
190: case FPC_SNAN:
191: fpsr |= FPSR_SNAN;
192: case FPC_QNAN:
193: /* dst = NaN */
194: exp = 0x7fff;
195: m0 = m1 = 0xffffffff;
196: break;
197: case FPC_ZERO:
198: case FPC_NUM:
199: if ((0 < exp && exp < 0x7fff) ||
200: (exp == 0 && (m0 | m1) != 0)) {
201: /* normal or denormal */
202: exp += scale;
203: if (exp < 0) {
204: /* underflow */
205: u_int grs; /* guard, round and sticky */
206:
207: exp = 0;
208: grs = m1 << (32 + exp);
209: m1 = m0 << (32 + exp) | m1 >> -exp;
210: m0 >>= -exp;
211: if (grs != 0) {
212: fpsr |= FPSR_INEX2;
213:
214: switch (fe->fe_fpcr & 0x30) {
215: case FPCR_MINF:
216: if (sign != 0) {
217: if (++m1 == 0 &&
218: ++m0 == 0) {
219: m0 = 0x80000000;
220: exp++;
221: }
222: }
223: break;
224: case FPCR_NEAR:
225: if (grs == 0x80000000) {
226: /* tie */
227: if ((m1 & 1) &&
228: ++m1 == 0 &&
229: ++m0 == 0) {
230: m0 = 0x80000000;
231: exp++;
232: }
233: } else if (grs & 0x80000000) {
234: if (++m1 == 0 &&
235: ++m0 == 0) {
236: m0 = 0x80000000;
237: exp++;
238: }
239: }
240: break;
241: case FPCR_PINF:
242: if (sign == 0) {
243: if (++m1 == 0 &&
244: ++m0 == 0) {
245: m0 = 0x80000000;
246: exp++;
247: }
248: }
249: break;
250: case FPCR_ZERO:
251: break;
252: }
253: }
254: if (exp == 0 && (m0 & 0x80000000) == 0) {
255: fpsr |= FPSR_UNFL;
256: if ((m0 | m1) == 0) {
257: fpsr |= FPSR_ZERO;
258: }
259: }
260: } else if (exp >= 0x7fff) {
261: /* overflow --> result = Inf */
262: /* but first, try to normalize in case it's an unnormalized */
263: while ((m0 & 0x80000000) == 0) {
264: exp--;
265: m0 = (m0 << 1) | (m1 >> 31);
266: m1 = m1 << 1;
267: }
268: /* if it's still too large, then return Inf */
269: if (exp >= 0x7fff) {
270: exp = 0x7fff;
271: m0 = m1 = 0;
272: fpsr |= FPSR_OVFL | FPSR_INF;
273: }
274: } else if ((m0 & 0x80000000) == 0) {
275: /*
276: * it's a denormal; we try to normalize but
277: * result may and may not be a normal.
278: */
279: while (exp > 0 && (m0 & 0x80000000) == 0) {
280: exp--;
281: m0 = (m0 << 1) | (m1 >> 31);
282: m1 = m1 << 1;
283: }
284: if ((m0 & 0x80000000) == 0) {
285: fpsr |= FPSR_UNFL;
286: }
287: } /* exp in range and mantissa normalized */
288: } else if (exp == 0 && m0 == 0 && m1 == 0) {
289: /* dst is Zero */
290: fpsr |= FPSR_ZERO;
291: } /* else we know exp == 0x7fff */
292: else if ((m0 | m1) == 0) {
293: fpsr |= FPSR_INF;
294: } else if ((m0 & 0x40000000) == 0) {
295: /* a signaling NaN */
296: fpsr |= FPSR_NAN | FPSR_SNAN;
297: } else {
298: /* a quiet NaN */
299: fpsr |= FPSR_NAN;
300: }
301: break;
302: case FPC_INF:
303: /* dst = NaN */
304: exp = 0x7fff;
305: m0 = m1 = 0xffffffff;
306: fpsr |= FPSR_OPERR | FPSR_NAN;
307: break;
308: default:
309: #ifdef DEBUG
310: panic("fpu_emul_fscale: invalid fp class");
311: #endif
312: break;
313: }
314:
315: /* store the result */
316: fpregs[regnum * 3] = sign | (exp << 16);
317: fpregs[regnum * 3 + 1] = m0;
318: fpregs[regnum * 3 + 2] = m1;
319:
320: if (sign) {
321: fpsr |= FPSR_NEG;
322: }
323:
324: /* update fpsr according to the result of operation */
325: fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr;
326:
327: #if DEBUG_FPE
328: printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n",
329: fe->fe_fpsr, fe->fe_fpcr);
330: #endif
331:
332: return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig;
333: }
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