Annotation of sys/arch/m68k/fpe/fpu_explode.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: fpu_explode.c,v 1.6 2006/06/11 20:43:28 miod Exp $ */
2: /* $NetBSD: fpu_explode.c,v 1.6 2003/10/23 15:07:30 kleink Exp $ */
3:
4: /*
5: * Copyright (c) 1992, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This software was developed by the Computer Systems Engineering group
9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10: * contributed to Berkeley.
11: *
12: * All advertising materials mentioning features or use of this software
13: * must display the following acknowledgement:
14: * This product includes software developed by the University of
15: * California, Lawrence Berkeley Laboratory.
16: *
17: * Redistribution and use in source and binary forms, with or without
18: * modification, are permitted provided that the following conditions
19: * are met:
20: * 1. Redistributions of source code must retain the above copyright
21: * notice, this list of conditions and the following disclaimer.
22: * 2. Redistributions in binary form must reproduce the above copyright
23: * notice, this list of conditions and the following disclaimer in the
24: * documentation and/or other materials provided with the distribution.
25: * 3. Neither the name of the University nor the names of its contributors
26: * may be used to endorse or promote products derived from this software
27: * without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39: * SUCH DAMAGE.
40: *
41: * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93
42: */
43:
44: /*
45: * FPU subroutines: `explode' the machine's `packed binary' format numbers
46: * into our internal format.
47: */
48:
49: #include <sys/types.h>
50: #include <sys/systm.h>
51:
52: #include <machine/ieee.h>
53: #include <machine/reg.h>
54:
55: #include <m68k/fpe/fpu_arith.h>
56: #include <m68k/fpe/fpu_emulate.h>
57:
58:
59: /* Conversion to internal format -- note asymmetry. */
60: int fpu_itof(struct fpn *fp, u_int i);
61: int fpu_stof(struct fpn *fp, u_int i);
62: int fpu_dtof(struct fpn *fp, u_int i, u_int j);
63: int fpu_xtof(struct fpn *fp, u_int i, u_int j, u_int k);
64:
65: /*
66: * N.B.: in all of the following, we assume the FP format is
67: *
68: * ---------------------------
69: * | s | exponent | fraction |
70: * ---------------------------
71: *
72: * (which represents -1**s * 1.fraction * 2**exponent), so that the
73: * sign bit is way at the top (bit 31), the exponent is next, and
74: * then the remaining bits mark the fraction. A zero exponent means
75: * zero or denormalized (0.fraction rather than 1.fraction), and the
76: * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
77: *
78: * Since the sign bit is always the topmost bit---this holds even for
79: * integers---we set that outside all the *tof functions. Each function
80: * returns the class code for the new number (but note that we use
81: * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
82: */
83:
84: /*
85: * int -> fpn.
86: */
87: int
88: fpu_itof(fp, i)
89: struct fpn *fp;
90: u_int i;
91: {
92:
93: if (i == 0)
94: return (FPC_ZERO);
95: /*
96: * The value FP_1 represents 2^FP_LG, so set the exponent
97: * there and let normalization fix it up. Convert negative
98: * numbers to sign-and-magnitude. Note that this relies on
99: * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
100: */
101: fp->fp_exp = FP_LG;
102: fp->fp_mant[0] = (int)i < 0 ? -i : i;
103: fp->fp_mant[1] = 0;
104: fp->fp_mant[2] = 0;
105: fpu_norm(fp);
106: return (FPC_NUM);
107: }
108:
109: #define mask(nbits) ((1 << (nbits)) - 1)
110:
111: /*
112: * All external floating formats convert to internal in the same manner,
113: * as defined here. Note that only normals get an implied 1.0 inserted.
114: */
115: #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
116: if (exp == 0) { \
117: if (allfrac == 0) \
118: return (FPC_ZERO); \
119: fp->fp_exp = 1 - expbias; \
120: fp->fp_mant[0] = f0; \
121: fp->fp_mant[1] = f1; \
122: fp->fp_mant[2] = f2; \
123: fpu_norm(fp); \
124: return (FPC_NUM); \
125: } \
126: if (exp == (2 * expbias + 1)) { \
127: if (allfrac == 0) \
128: return (FPC_INF); \
129: fp->fp_mant[0] = f0; \
130: fp->fp_mant[1] = f1; \
131: fp->fp_mant[2] = f2; \
132: return (FPC_QNAN); \
133: } \
134: fp->fp_exp = exp - expbias; \
135: fp->fp_mant[0] = FP_1 | f0; \
136: fp->fp_mant[1] = f1; \
137: fp->fp_mant[2] = f2; \
138: return (FPC_NUM)
139:
140: /*
141: * 32-bit single precision -> fpn.
142: * We assume a single occupies at most (64-FP_LG) bits in the internal
143: * format: i.e., needs at most fp_mant[0] and fp_mant[1].
144: */
145: int
146: fpu_stof(fp, i)
147: struct fpn *fp;
148: u_int i;
149: {
150: int exp;
151: u_int frac, f0, f1;
152: #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
153:
154: exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
155: frac = i & mask(SNG_FRACBITS);
156: f0 = frac >> SNG_SHIFT;
157: f1 = frac << (32 - SNG_SHIFT);
158: FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
159: }
160:
161: /*
162: * 64-bit double -> fpn.
163: * We assume this uses at most (96-FP_LG) bits.
164: */
165: int
166: fpu_dtof(fp, i, j)
167: struct fpn *fp;
168: u_int i, j;
169: {
170: int exp;
171: u_int frac, f0, f1, f2;
172: #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
173:
174: exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
175: frac = i & mask(DBL_FRACBITS - 32);
176: f0 = frac >> DBL_SHIFT;
177: f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
178: f2 = j << (32 - DBL_SHIFT);
179: frac |= j;
180: FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
181: }
182:
183: /*
184: * 96-bit extended -> fpn.
185: */
186: int
187: fpu_xtof(fp, i, j, k)
188: struct fpn *fp;
189: u_int i, j, k;
190: {
191: int exp;
192: u_int frac, f0, f1, f2;
193: #define EXT_SHIFT (EXT_FRACBITS - 1 - 32 - FP_LG)
194:
195: exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);
196: f0 = j >> EXT_SHIFT;
197: f1 = (j << (32 - EXT_SHIFT)) | (k >> EXT_SHIFT);
198: f2 = k << (32 - EXT_SHIFT);
199: frac = j | k;
200:
201: /* m68k extended does not imply denormal by exp==0 */
202: if (exp == 0) {
203: if (frac == 0)
204: return (FPC_ZERO);
205: fp->fp_exp = - EXT_EXP_BIAS;
206: fp->fp_mant[0] = f0;
207: fp->fp_mant[1] = f1;
208: fp->fp_mant[2] = f2;
209: fpu_norm(fp);
210: return (FPC_NUM);
211: }
212: if (exp == (2 * EXT_EXP_BIAS + 1)) {
213: if (frac == 0)
214: return (FPC_INF);
215: fp->fp_mant[0] = f0;
216: fp->fp_mant[1] = f1;
217: fp->fp_mant[2] = f2;
218: return (FPC_QNAN);
219: }
220: fp->fp_exp = exp - EXT_EXP_BIAS;
221: fp->fp_mant[0] = FP_1 | f0;
222: fp->fp_mant[1] = f1;
223: fp->fp_mant[2] = f2;
224: return (FPC_NUM);
225: }
226:
227: /*
228: * Explode the contents of a memory operand.
229: */
230: void
231: fpu_explode(fe, fp, type, space)
232: struct fpemu *fe;
233: struct fpn *fp;
234: int type;
235: u_int *space;
236: {
237: u_int s;
238:
239: s = space[0];
240: fp->fp_sign = s >> 31;
241: fp->fp_sticky = 0;
242: switch (type) {
243:
244: case FTYPE_BYT:
245: s >>= 8;
246: case FTYPE_WRD:
247: s >>= 16;
248: case FTYPE_LNG:
249: s = fpu_itof(fp, s);
250: break;
251:
252: case FTYPE_SNG:
253: s = fpu_stof(fp, s);
254: break;
255:
256: case FTYPE_DBL:
257: s = fpu_dtof(fp, s, space[1]);
258: break;
259:
260: case FTYPE_EXT:
261: s = fpu_xtof(fp, s, space[1], space[2]);
262: break;
263:
264: default:
265: panic("fpu_explode");
266: }
267: if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
268: /*
269: * Input is a signalling NaN. All operations that return
270: * an input NaN operand put it through a ``NaN conversion'',
271: * which basically just means ``turn on the quiet bit''.
272: * We do this here so that all NaNs internally look quiet
273: * (we can tell signalling ones by their class).
274: */
275: fp->fp_mant[0] |= FP_QUIETBIT;
276: fe->fe_fpsr |= FPSR_SNAN; /* assert SNAN exception */
277: s = FPC_SNAN;
278: }
279: fp->fp_class = s;
280: }
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to fpu_explode.c CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / m68k / fpe