Annotation of sys/arch/m68k/060sp/fskeletn.s, Revision 1.1.1.1
1.1 nbrk 1: #
2: # $OpenBSD: fskeletn.s,v 1.2 1996/05/30 22:14:31 niklas Exp $
3: # $NetBSD: fskeletn.s,v 1.2 1996/05/15 19:48:30 is Exp $
4: #
5:
6: #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7: # MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
8: # M68000 Hi-Performance Microprocessor Division
9: # M68060 Software Package Production Release
10: #
11: # M68060 Software Package Copyright (C) 1993, 1994, 1995, 1996 Motorola Inc.
12: # All rights reserved.
13: #
14: # THE SOFTWARE is provided on an "AS IS" basis and without warranty.
15: # To the maximum extent permitted by applicable law,
16: # MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
17: # INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
18: # FOR A PARTICULAR PURPOSE and any warranty against infringement with
19: # regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
20: # and any accompanying written materials.
21: #
22: # To the maximum extent permitted by applicable law,
23: # IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
24: # (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
25: # BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
26: # ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
27: #
28: # Motorola assumes no responsibility for the maintenance and support
29: # of the SOFTWARE.
30: #
31: # You are hereby granted a copyright license to use, modify, and distribute the
32: # SOFTWARE so long as this entire notice is retained without alteration
33: # in any modified and/or redistributed versions, and that such modified
34: # versions are clearly identified as such.
35: # No licenses are granted by implication, estoppel or otherwise under any
36: # patents or trademarks of Motorola, Inc.
37: #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
38:
39: #
40: # fskeleton.s
41: #
42: # This file contains:
43: # (1) example "Call-out"s
44: # (2) example package entry code
45: # (3) example "Call-out" table
46: #
47:
48:
49: #################################
50: # (1) EXAMPLE CALL-OUTS #
51: # #
52: # _060_fpsp_done() #
53: # _060_real_ovfl() #
54: # _060_real_unfl() #
55: # _060_real_operr() #
56: # _060_real_snan() #
57: # _060_real_dz() #
58: # _060_real_inex() #
59: # _060_real_bsun() #
60: # _060_real_fline() #
61: # _060_real_fpu_disabled() #
62: # _060_real_trap() #
63: #################################
64:
65: #
66: # _060_fpsp_done():
67: #
68: # This is the main exit point for the 68060 Floating-Point
69: # Software Package. For a normal exit, all 060FPSP routines call this
70: # routine. The operating system can do system dependent clean-up or
71: # simply execute an "rte" as with the sample code below.
72: #
73: global _060_fpsp_done
74: _060_fpsp_done:
75: rte
76:
77: #
78: # _060_real_ovfl():
79: #
80: # This is the exit point for the 060FPSP when an enabled overflow exception
81: # is present. The routine below should point to the operating system handler
82: # for enabled overflow conditions. The exception stack frame is an overflow
83: # stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
84: #
85: # The sample routine below simply clears the exception status bit and
86: # does an "rte".
87: #
88: global _060_real_ovfl
89: _060_real_ovfl:
90: fsave -(%sp)
91: mov.w &0x6000,0x2(%sp)
92: frestore (%sp)+
93: rte
94:
95: #
96: # _060_real_unfl():
97: #
98: # This is the exit point for the 060FPSP when an enabled underflow exception
99: # is present. The routine below should point to the operating system handler
100: # for enabled underflow conditions. The exception stack frame is an underflow
101: # stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
102: #
103: # The sample routine below simply clears the exception status bit and
104: # does an "rte".
105: #
106: global _060_real_unfl
107: _060_real_unfl:
108: fsave -(%sp)
109: mov.w &0x6000,0x2(%sp)
110: frestore (%sp)+
111: rte
112:
113: #
114: # _060_real_operr():
115: #
116: # This is the exit point for the 060FPSP when an enabled operand error exception
117: # is present. The routine below should point to the operating system handler
118: # for enabled operand error exceptions. The exception stack frame is an operand error
119: # stack frame. The FP state frame holds the source operand of the faulting
120: # instruction.
121: #
122: # The sample routine below simply clears the exception status bit and
123: # does an "rte".
124: #
125: global _060_real_operr
126: _060_real_operr:
127: fsave -(%sp)
128: mov.w &0x6000,0x2(%sp)
129: frestore (%sp)+
130: rte
131:
132: #
133: # _060_real_snan():
134: #
135: # This is the exit point for the 060FPSP when an enabled signalling NaN exception
136: # is present. The routine below should point to the operating system handler
137: # for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN
138: # stack frame. The FP state frame holds the source operand of the faulting
139: # instruction.
140: #
141: # The sample routine below simply clears the exception status bit and
142: # does an "rte".
143: #
144: global _060_real_snan
145: _060_real_snan:
146: fsave -(%sp)
147: mov.w &0x6000,0x2(%sp)
148: frestore (%sp)+
149: rte
150:
151: #
152: # _060_real_dz():
153: #
154: # This is the exit point for the 060FPSP when an enabled divide-by-zero exception
155: # is present. The routine below should point to the operating system handler
156: # for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero
157: # stack frame. The FP state frame holds the source operand of the faulting
158: # instruction.
159: #
160: # The sample routine below simply clears the exception status bit and
161: # does an "rte".
162: #
163: global _060_real_dz
164: _060_real_dz:
165: fsave -(%sp)
166: mov.w &0x6000,0x2(%sp)
167: frestore (%sp)+
168: rte
169:
170: #
171: # _060_real_inex():
172: #
173: # This is the exit point for the 060FPSP when an enabled inexact exception
174: # is present. The routine below should point to the operating system handler
175: # for enabled inexact exceptions. The exception stack frame is an inexact
176: # stack frame. The FP state frame holds the source operand of the faulting
177: # instruction.
178: #
179: # The sample routine below simply clears the exception status bit and
180: # does an "rte".
181: #
182: global _060_real_inex
183: _060_real_inex:
184: fsave -(%sp)
185: mov.w &0x6000,0x2(%sp)
186: frestore (%sp)+
187: rte
188:
189: #
190: # _060_real_bsun():
191: #
192: # This is the exit point for the 060FPSP when an enabled bsun exception
193: # is present. The routine below should point to the operating system handler
194: # for enabled bsun exceptions. The exception stack frame is a bsun
195: # stack frame.
196: #
197: # The sample routine below clears the exception status bit, clears the NaN
198: # bit in the FPSR, and does an "rte". The instruction that caused the
199: # bsun will now be re-executed but with the NaN FPSR bit cleared.
200: #
201: global _060_real_bsun
202: _060_real_bsun:
203: fsave -(%sp)
204:
205: fmov.l %fpsr,-(%sp)
206: andi.b &0xfe,(%sp)
207: fmov.l (%sp)+,%fpsr
208:
209: add.l &0xc,%sp
210: rte
211:
212: #
213: # _060_real_fline():
214: #
215: # This is the exit point for the 060FPSP when an F-Line Illegal exception is
216: # encountered. Three different types of exceptions can enter the F-Line exception
217: # vector number 11: FP Unimplemented Instructions, FP implemented instructions when
218: # the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
219: # _fpsp_fline() distinguishes between the three and acts appropriately. F-Line
220: # Illegals branch here.
221: #
222: global _060_real_fline
223: _060_real_fline:
224: bra.b _060_real_fline
225:
226: #
227: # _060_real_fpu_disabled():
228: #
229: # This is the exit point for the 060FPSP when an FPU disabled exception is
230: # encountered. Three different types of exceptions can enter the F-Line exception
231: # vector number 11: FP Unimplemented Instructions, FP implemented instructions when
232: # the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
233: # _fpsp_fline() distinguishes between the three and acts appropriately. FPU disabled
234: # exceptions branch here.
235: #
236: # The sample code below enables the FPU, sets the PC field in the exception stack
237: # frame to the PC of the instruction causing the exception, and does an "rte".
238: # The execution of the instruction then proceeds with an enabled floating-point
239: # unit.
240: #
241: global _060_real_fpu_disabled
242: _060_real_fpu_disabled:
243: mov.l %d0,-(%sp) # enabled the fpu
244: movc %pcr,%d0
245: bclr &0x1,%d0
246: movc %d0,%pcr
247: mov.l (%sp)+,%d0
248:
249: mov.l 0xc(%sp),0x2(%sp) # set "Current PC"
250: rte
251:
252: #
253: # _060_real_trap():
254: #
255: # This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
256: # discovers that the trap condition is true and it should branch to the operating
257: # system handler for the trap exception vector number 7.
258: #
259: # The sample code below simply executes an "rte".
260: #
261: global _060_real_trap
262: _060_real_trap:
263: rte
264:
265: #############################################################################
266:
267: ##################################
268: # (2) EXAMPLE PACKAGE ENTRY CODE #
269: ##################################
270:
271: global _060_fpsp_snan
272: _060_fpsp_snan:
273: bra.l _FP_CALL_TOP+0x80+0x00
274:
275: global _060_fpsp_operr
276: _060_fpsp_operr:
277: bra.l _FP_CALL_TOP+0x80+0x08
278:
279: global _060_fpsp_ovfl
280: _060_fpsp_ovfl:
281: bra.l _FP_CALL_TOP+0x80+0x10
282:
283: global _060_fpsp_unfl
284: _060_fpsp_unfl:
285: bra.l _FP_CALL_TOP+0x80+0x18
286:
287: global _060_fpsp_dz
288: _060_fpsp_dz:
289: bra.l _FP_CALL_TOP+0x80+0x20
290:
291: global _060_fpsp_inex
292: _060_fpsp_inex:
293: bra.l _FP_CALL_TOP+0x80+0x28
294:
295: global _060_fpsp_fline
296: _060_fpsp_fline:
297: bra.l _FP_CALL_TOP+0x80+0x30
298:
299: global _060_fpsp_unsupp
300: _060_fpsp_unsupp:
301: bra.l _FP_CALL_TOP+0x80+0x38
302:
303: global _060_fpsp_effadd
304: _060_fpsp_effadd:
305: bra.l _FP_CALL_TOP+0x80+0x40
306:
307: #############################################################################
308:
309: ################################
310: # (3) EXAMPLE CALL-OUT SECTION #
311: ################################
312:
313: # The size of this section MUST be 128 bytes!!!
314:
315: global _FP_CALL_TOP
316: _FP_CALL_TOP:
317: long _060_real_bsun - _FP_CALL_TOP
318: long _060_real_snan - _FP_CALL_TOP
319: long _060_real_operr - _FP_CALL_TOP
320: long _060_real_ovfl - _FP_CALL_TOP
321: long _060_real_unfl - _FP_CALL_TOP
322: long _060_real_dz - _FP_CALL_TOP
323: long _060_real_inex - _FP_CALL_TOP
324: long _060_real_fline - _FP_CALL_TOP
325: long _060_real_fpu_disabled - _FP_CALL_TOP
326: long _060_real_trap - _FP_CALL_TOP
327: long _060_real_trace - _FP_CALL_TOP
328: long _060_real_access - _FP_CALL_TOP
329: long _060_fpsp_done - _FP_CALL_TOP
330:
331: long 0x00000000, 0x00000000, 0x00000000
332:
333: long _060_imem_read - _FP_CALL_TOP
334: long _060_dmem_read - _FP_CALL_TOP
335: long _060_dmem_write - _FP_CALL_TOP
336: long _060_imem_read_word - _FP_CALL_TOP
337: long _060_imem_read_long - _FP_CALL_TOP
338: long _060_dmem_read_byte - _FP_CALL_TOP
339: long _060_dmem_read_word - _FP_CALL_TOP
340: long _060_dmem_read_long - _FP_CALL_TOP
341: long _060_dmem_write_byte - _FP_CALL_TOP
342: long _060_dmem_write_word - _FP_CALL_TOP
343: long _060_dmem_write_long - _FP_CALL_TOP
344:
345: long 0x00000000
346:
347: long 0x00000000, 0x00000000, 0x00000000, 0x00000000
348:
349: #############################################################################
350:
351: # 060 FPSP KERNEL PACKAGE NEEDS TO GO HERE!!!
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to fskeletn.s CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / m68k / 060sp