Annotation of sys/arch/luna88k/include/board.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: board.h,v 1.7 2007/05/12 19:59:01 miod Exp $ */
! 2: /*
! 3: * Mach Operating System
! 4: * Copyright (c) 1993-1991 Carnegie Mellon University
! 5: * Copyright (c) 1991 OMRON Corporation
! 6: * All Rights Reserved.
! 7: *
! 8: * Permission to use, copy, modify and distribute this software and its
! 9: * documentation is hereby granted, provided that both the copyright
! 10: * notice and this permission notice appear in all copies of the
! 11: * software, derivative works or modified versions, and any portions
! 12: * thereof, and that both notices appear in supporting documentation.
! 13: *
! 14: * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
! 15: * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND
! 16: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 17: *
! 18: * Carnegie Mellon requests users of this software to return to
! 19: *
! 20: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
! 21: * School of Computer Science
! 22: * Carnegie Mellon University
! 23: * Pittsburgh PA 15213-3890
! 24: *
! 25: * any improvements or extensions that they make and grant Carnegie the
! 26: * rights to redistribute these changes.
! 27: */
! 28:
! 29: #ifndef __LUNA88K_BOARD_H__
! 30: #define __LUNA88K_BOARD_H__
! 31:
! 32: /*
! 33: * OMRON SX9100DT CPU board constants
! 34: */
! 35:
! 36: /*
! 37: * Something to put append a 'U' to a long constant if it's C so that
! 38: * it'll be unsigned in both ANSI and traditional.
! 39: */
! 40: #if defined(_LOCORE)
! 41: #define U(num) num
! 42: #elif defined(__STDC__)
! 43: #define U(num) num ## U
! 44: #else
! 45: #define U(num) num/**/U
! 46: #endif
! 47: #define UDEFINED
! 48:
! 49: /* machtype values */
! 50: #define LUNA_88K 0x1
! 51: #define LUNA_88K2 0x2
! 52:
! 53: #define SYSV_BASE U(0x00000000) /* system virtual base */
! 54: #define VEQR_ADDR U(0x00000000)
! 55:
! 56: #define OBIO_START U(0x41000000)
! 57: #define OBIO_SIZE U(0xBf000000)
! 58:
! 59: #define OBIO1_BASE U(0x41000000) /* on board i/o 1 base */
! 60: #define OBIO1_SPACE U(0x1f000000) /* on board i/o 1 space */
! 61: #define OBIO2_BASE U(0x61000000) /* on board i/o 2 base */
! 62: #define OBIO2_SPACE U(0x1f000000) /* on board i/o 2 space */
! 63: #define OBIO3_BASE U(0x80000000) /* on board i/o 3 base */
! 64: #define OBIO3_SPACE U(0x80000000) /* on board i/o 3 space */
! 65:
! 66: #define MAXU_ADDR U(0x40000000) /* size of user virtual space */
! 67: #define MAXPHYSMEM U(0x10000000) /* max physical memory */
! 68:
! 69: #define PROM_ADDR U(0x41000000) /* PROM */
! 70: #define PROM_SPACE U(0x00040000)
! 71: #define NVRAM_ADDR U(0x45000000) /* Non Volatile */
! 72: #define NVRAM_SPACE U(0x00001FDC)
! 73: #define FUSE_ROM_ADDR U(0x43000000) /* FUSE_ROM */
! 74: #define FUSE_ROM_SPACE 1024
! 75: #define OBIO_CAL_CTL U(0x45001FE0) /* calendar control register */
! 76: #define OBIO_CAL_SEC U(0x45001FE4) /* seconds */
! 77: #define OBIO_CAL_MIN U(0x45001FE8) /* minutes */
! 78: #define OBIO_CAL_HOUR U(0x45001FEC) /* hours */
! 79: #define OBIO_CAL_DOW U(0x45001FF0) /* Day Of the Week */
! 80: #define OBIO_CAL_DAY U(0x45001FF4) /* days */
! 81: #define OBIO_CAL_MON U(0x45001FF8) /* months */
! 82: #define OBIO_CAL_YEAR U(0x45001FFC) /* years */
! 83: #define NVRAM_ADDR_88K2 U(0x47000000) /* Non Volatile RAM area for LUNA-88K2 */
! 84: #define OBIO_PIO0_BASE U(0x49000000) /* PIO-0 */
! 85: #define OBIO_PIO0_SPACE U(0x0000000C)
! 86: #define OBIO_PIO0A U(0x49000000) /* PIO-0 port A */
! 87: #define OBIO_PIO0B U(0x49000004) /* PIO-0 port B */
! 88: #define OBIO_PIO0C U(0x49000008) /* PIO-0 port C*/
! 89: #define OBIO_PIO0 U(0x4900000C) /* PIO-0 control */
! 90: #define OBIO_PIO1_BASE U(0x4D000000) /* PIO-1 */
! 91: #define OBIO_PIO1_SPACE U(0x0000000C)
! 92: #define OBIO_PIO1A U(0x4D000000) /* PIO-1 port A */
! 93: #define OBIO_PIO1B U(0x4D000004) /* PIO-1 port B */
! 94: #define OBIO_PIO1C U(0x4D000008) /* PIO-1 port C*/
! 95: #define OBIO_PIO1 U(0x4D00000C) /* PIO-1 control */
! 96: #define OBIO_SIO U(0x51000000) /* SIO */
! 97: #define OBIO_TAS U(0x61000000) /* TAS register */
! 98: #define OBIO_CLOCK0 U(0x63000000) /* system clock CPU 0 */
! 99: #define OBIO_CLOCK1 U(0x63000004) /* system clock CPU 1 */
! 100: #define OBIO_CLOCK2 U(0x63000008) /* system clock CPU 2 */
! 101: #define OBIO_CLOCK3 U(0x6300000C) /* system clock CPU 3 */
! 102: #define OBIO_CLK_INTR 31 /* system clock interrupt flag */
! 103: #define INT_ST_MASK0 U(0x65000000) /* interrupt status register CPU 0 */
! 104: #define INT_ST_MASK1 U(0x65000004) /* interrupt status register CPU 1 */
! 105: #define INT_ST_MASK2 U(0x65000008) /* interrupt status register CPU 2 */
! 106: #define INT_ST_MASK3 U(0x6500000C) /* interrupt status register CPU 3 */
! 107: #define INT_LEVEL 8 /* # of intrrupt level + 1 */
! 108: #define INT_SET_LV7 U(0x00000000) /* disable interrupts */
! 109: #define INT_SET_LV6 U(0x00000000) /* enable level 7 */
! 110: #define INT_SET_LV5 U(0x80000000) /* enable level 7-6 */
! 111: #define INT_SET_LV4 U(0xC0000000) /* enable level 7-5 */
! 112: #define INT_SET_LV3 U(0xE0000000) /* enable level 7-4 */
! 113: #define INT_SET_LV2 U(0xF0000000) /* enable level 7-3 */
! 114: #define INT_SET_LV1 U(0xF8000000) /* enable level 7-2 */
! 115: #define INT_SET_LV0 U(0xFC000000) /* enable interrupts */
! 116: #define INT_SLAVE_MASK U(0x84000000) /* slave can only enable 6 and 1 */
! 117: #define INT_CLOCK_MASK 0xBFFFFFFF /* mask clock */
! 118:
! 119: #define NON_MASKABLE_LEVEL 7 /* non-maskable-interrupt (abort) */
! 120: #define CLOCK_INT_LEVEL 6 /* clock interrupt level */
! 121: #define SOFT_INT_LEVEL 1 /* software interrupt level */
! 122: #define SOFT_INT0 U(0x69000000) /* software interrupt CPU 0 */
! 123: #define SOFT_INT1 U(0x69000004) /* software interrupt CPU 1 */
! 124: #define SOFT_INT2 U(0x69000008) /* software interrupt CPU 2 */
! 125: #define SOFT_INT3 U(0x6900000C) /* software interrupt CPU 3 */
! 126: #define SOFT_INT_FLAG0 U(0x6B000000) /* sfotware interrupt flag CPU 0 */
! 127: #define SOFT_INT_FLAG1 U(0x6B000000) /* sfotware interrupt flag CPU 1 */
! 128: #define SOFT_INT_FLAG2 U(0x6B000000) /* sfotware interrupt flag CPU 2 */
! 129: #define SOFT_INT_FLAG3 U(0x6B000000) /* sfotware interrupt flag CPU 3 */
! 130: #define SOFT_INT_BIT 31 /* software interrupt flag bit */
! 131: #define RESET_CPU0 U(0x6D000000) /* reset CPU 0 */
! 132: #define RESET_CPU1 U(0x6D000004) /* reset CPU 1 */
! 133: #define RESET_CPU2 U(0x6D000008) /* reset CPU 2 */
! 134: #define RESET_CPU3 U(0x6D00000C) /* reset CPU 3 */
! 135: #define RESET_CPU_ALL U(0x6D000010) /* reset ALL CPUs */
! 136: #define TRI_PORT_RAM U(0x71000000) /* 3 port RAM */
! 137: #define TRI_PORT_RAM_SPACE 0x20000
! 138: #define EXT_A_ADDR U(0x81000000) /* extension board A */
! 139: #define EXT_A_SPACE U(0x02000000)
! 140: #define EU_BASE U(0x81fe0000) /* VME expand board */
! 141: #define EXT_B_ADDR U(0x83000000) /* extension board B */
! 142: #define EXT_B_SPACE U(0x01000000)
! 143: #define PC_BASE U(0x90000000) /* pc-98 extension board */
! 144: #define PC_SPACE U(0x02000000)
! 145:
! 146: #define MROM_ADDR U(0xA1000000) /* Mask ROM address */
! 147: #define MROM_SPACE 0x400000
! 148: #define BMAP_START U(0xB1000000) /* Bitmap start address */
! 149: #define BMAP_SPACE (BMAP_END - BMAP_START)
! 150: #define BMAP_RFCNT U(0xB1000000) /* RFCNT register */
! 151: #define BMAP_BMSEL U(0xB1040000) /* BMSEL register */
! 152: #define BMAP_BMP U(0xB1080000) /* common bitmap plane */
! 153: #define BMAP_BMAP0 U(0xB10C0000) /* bitmap plane 0 */
! 154: #define BMAP_BMAP1 U(0xB1100000) /* bitmap plane 1 */
! 155: #define BMAP_BMAP2 U(0xB1140000) /* bitmap plane 2 */
! 156: #define BMAP_BMAP3 U(0xB1180000) /* bitmap plane 3 */
! 157: #define BMAP_BMAP4 U(0xB11C0000) /* bitmap plane 4 */
! 158: #define BMAP_BMAP5 U(0xB1200000) /* bitmap plane 5 */
! 159: #define BMAP_BMAP6 U(0xB1240000) /* bitmap plane 6 */
! 160: #define BMAP_BMAP7 U(0xB1280000) /* bitmap plane 7 */
! 161: #define BMAP_FN U(0xB12C0000) /* common bitmap function */
! 162: #define BMAP_FN0 U(0xB1300000) /* bitmap function 0 */
! 163: #define BMAP_FN1 U(0xB1340000) /* bitmap function 1 */
! 164: #define BMAP_FN2 U(0xB1380000) /* bitmap function 2 */
! 165: #define BMAP_FN3 U(0xB13C0000) /* bitmap function 3 */
! 166: #define BMAP_FN4 U(0xB1400000) /* bitmap function 4 */
! 167: #define BMAP_FN5 U(0xB1440000) /* bitmap function 5 */
! 168: #define BMAP_FN6 U(0xB1480000) /* bitmap function 6 */
! 169: #define BMAP_FN7 U(0xB14C0000) /* bitmap function 7 */
! 170: #define BMAP_END U(0xB1500000)
! 171: #define BMAP_END24P U(0xB1800000) /* end of 24p framemem */
! 172: #define BMAP_PALLET0 U(0xC0000000) /* color pallet */
! 173: #define BMAP_PALLET1 U(0xC1000000) /* color pallet */
! 174: #define BMAP_PALLET2 U(0xC1100000) /* color pallet */
! 175: #define BOARD_CHECK_REG U(0xD0000000) /* board check register */
! 176: #define BMAP_CRTC U(0xD1000000) /* CTRC-II */
! 177: #define BMAP_IDENTROM U(0xD1800000) /* bitmap-board identify ROM */
! 178: #define SCSI_ADDR U(0xE1000000) /* SCSI address */
! 179: #define LANCE_ADDR U(0xF1000000) /* LANCE */
! 180: #define EXT_IACK_ADDR 0xFFFFFFF7 /* IACK Space for Extended Board */
! 181:
! 182: #define VDMA_STD(x) ((int)(x))
! 183:
! 184: #define CMMU_I0 U(0xFFF07000) /* CMMU instruction cpu 0 */
! 185: #define CMMU_D0 U(0xFFF06000) /* CMMU data cpu 0 */
! 186: #define CMMU_I1 U(0xFFF05000) /* CMMU instruction cpu 1 */
! 187: #define CMMU_D1 U(0xFFF04000) /* CMMU data cpu 1 */
! 188: #define CMMU_I2 U(0xFFF03000) /* CMMU instruction cpu 2 */
! 189: #define CMMU_D2 U(0xFFF02000) /* CMMU data cpu 2 */
! 190: #define CMMU_I3 U(0xFFF01000) /* CMMU instruction cpu 3 */
! 191: #define CMMU_D3 U(0xFFF00000) /* CMMU data cpu 3 */
! 192:
! 193: #endif /* __LUNA88K_BOARD_H__ */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to board.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / luna88k / include