Annotation of sys/arch/luna88k/dev/sioreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: sioreg.h,v 1.1 2004/04/21 15:23:55 aoyama Exp $ */
! 2: /* $NetBSD: sioreg.h,v 1.1 2000/01/05 08:48:55 nisimura Exp $ */
! 3: /*
! 4: * Copyright (c) 1992 OMRON Corporation.
! 5: * Copyright (c) 1992, 1993
! 6: * The Regents of the University of California. All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to Berkeley by
! 9: * OMRON Corporation.
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. Redistributions in binary form must reproduce the above copyright
! 17: * notice, this list of conditions and the following disclaimer in the
! 18: * documentation and/or other materials provided with the distribution.
! 19: * 3. All advertising materials mentioning features or use of this software
! 20: * must display the following acknowledgement:
! 21: * This product includes software developed by the University of
! 22: * California, Berkeley and its contributors.
! 23: * 4. Neither the name of the University nor the names of its contributors
! 24: * may be used to endorse or promote products derived from this software
! 25: * without specific prior written permission.
! 26: *
! 27: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 28: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 29: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 30: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 31: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 32: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 33: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 34: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 35: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 36: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 37: * SUCH DAMAGE.
! 38: *
! 39: * @(#)sioreg.h 8.1 (Berkeley) 6/10/93
! 40: */
! 41:
! 42: #define WR0 0x00
! 43: #define WR1 0x01
! 44: #define WR2 0x02
! 45: #define WR3 0x03
! 46: #define WR4 0x04
! 47: #define WR5 0x05
! 48: #define WR6 0x06
! 49: #define WR7 0x07
! 50:
! 51: #define WR2A WR2
! 52: #define WR2B (WR2|0x10)
! 53:
! 54: #define RR0 0x08
! 55: #define RR1 0x09
! 56: #define RR2 0x0A
! 57: #define RR3 0x0B
! 58: #define RR4 0x0C
! 59:
! 60: #define RR2A RR2
! 61: #define RR2B (RR2|0x10)
! 62:
! 63: #define WR0_NOP 0x00 /* No Operation */
! 64: #define WR0_SNDABRT 0x08 /* Send Abort (HDLC) */
! 65: #define WR0_RSTINT 0x10 /* Reset External/Status Interrupt */
! 66: #define WR0_CHANRST 0x18 /* Channel Reset */
! 67: #define WR0_INTNXT 0x20 /* Enable Interrupt on Next Receive Character */
! 68: #define WR0_RSTPEND 0x28 /* Reset Transmitter Interrput/DMA Pending */
! 69: #define WR0_ERRRST 0x30 /* Error Reset */
! 70: #define WR0_ENDINTR 0x38 /* End of Interrupt */
! 71:
! 72: #define WR1_ESENBL 0x01 /* External/Status Interrupt Enable */
! 73: #define WR1_TXENBL 0x02 /* Tx Interrupt/DMA Enable */
! 74: #define WR1_STATVEC 0x04 /* Status Affects Vector (Only Chan-B) */
! 75: #define WR1_RXDSEBL 0x00 /* Rx Interrupt/DMA Disable */
! 76: #define WR1_RXFIRST 0x08 /* Interrupt only First Character Received */
! 77: #define WR1_RXALLS 0x10 /* Interrupt Every Characters Received (with Special Char.) */
! 78: #define WR1_RXALL 0x18 /* Interrupt Every Characters Received (without Special Char.) */
! 79:
! 80: #define WR2_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */
! 81: #define WR2_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */
! 82: #define WR2_VEC85_1 0x00 /* 8085 Vectored Mode - 1 */
! 83: #define WR2_VEC85_2 0x08 /* 8085 Vectored Mode - 2 */
! 84: #define WR2_VEC86 0x10 /* 8086 Vectored */
! 85: #define WR2_VEC85_3 0x18 /* 8085 Vectored Mode - 3 */
! 86:
! 87: #define WR3_RXENBL 0x01 /* Rx Enable */
! 88: #define WR3_RXCRC 0x08 /* Rx CRC Check */
! 89: #define WR3_AUTOEBL 0x20 /* Auto Enable (flow control for MODEM) */
! 90: #define WR3_RX5BIT 0x00 /* Rx Bits/Character: 5 Bits */
! 91: #define WR3_RX7BIT 0x40 /* Rx Bits/Character: 7 Bits */
! 92: #define WR3_RX6BIT 0x80 /* Rx Bits/Character: 6 Bits */
! 93: #define WR3_RX8BIT 0xc0 /* Rx Bits/Character: 8 Bits */
! 94:
! 95: #define WR4_NPARITY 0x00 /* No Parity */
! 96: #define WR4_PARENAB 0x01 /* Parity Enable */
! 97: #define WR4_OPARITY 0x01 /* Parity Odd */
! 98: #define WR4_EPARITY 0x02 /* Parity Even */
! 99: #define WR4_STOP1 0x04 /* Stop Bits (1bit) */
! 100: #define WR4_STOP15 0x08 /* Stop Bits (1.5bit) */
! 101: #define WR4_STOP2 0x0c /* Stop Bits (2bit) */
! 102: #define WR4_BAUD96 0x40 /* Clock Rate (9600 BAUD) */
! 103: #define WR4_BAUD48 0x80 /* Clock Rate (4800 BAUD) */
! 104: #define WR4_BAUD24 0xc0 /* Clock Rate (2400 BAUD) */
! 105:
! 106: #define WR5_TXCRC 0x01 /* Tx CRC Check */
! 107: #define WR5_RTS 0x02 /* Request To Send [RTS] */
! 108: #define WR5_TXENBL 0x08 /* Transmit Enable */
! 109: #define WR5_BREAK 0x10 /* Send Break [BRK] */
! 110: #define WR5_TX5BIT 0x00 /* Tx Bits/Character: 5 Bits */
! 111: #define WR5_TX7BIT 0x20 /* Tx Bits/Character: 7 Bits */
! 112: #define WR5_TX6BIT 0x40 /* Tx Bits/Character: 6 Bits */
! 113: #define WR5_TX8BIT 0x60 /* Tx Bits/Character: 8 Bits */
! 114: #define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */
! 115:
! 116: #define RR0_RXAVAIL 0x01 /* Rx Character Available */
! 117: #define RR0_INTRPEND 0x02 /* Interrupt Pending (Channel-A Only) */
! 118: #define RR0_TXEMPTY 0x04 /* Tx Buffer Empty */
! 119: #define RR0_DCD 0x08 /* Data Carrier Detect [DCD] */
! 120: #define RR0_SYNC 0x10 /* Synchronization */
! 121: #define RR0_CTS 0x20 /* Clear To Send [CTS] */
! 122: #define RR0_BREAK 0x80 /* Break Detected [BRK] */
! 123:
! 124: #define RR1_PARITY 0x10 /* Parity Error */
! 125: #define RR1_OVERRUN 0x20 /* Data Over Run */
! 126: #define RR1_FRAMING 0x40 /* Framing Error */
! 127:
! 128: #define RR_RXRDY 0x0100 /* Rx Character Available */
! 129: #define RR_INTRPEND 0x0200 /* Interrupt Pending (Channel-A Only) */
! 130: #define RR_TXRDY 0x0400 /* Tx Buffer Empty */
! 131: #define RR_DCD 0x0800 /* Data Carrier Detect [DCD] */
! 132: #define RR_SYNC 0x1000 /* Synchronization */
! 133: #define RR_CTS 0x2000 /* Clear To Send [CTS] */
! 134: #define RR_BREAK 0x8000 /* Break Detected */
! 135: #define RR_PARITY 0x0010 /* Parity Error */
! 136: #define RR_OVERRUN 0x0020 /* Data Over Run */
! 137: #define RR_FRAMING 0x0040 /* Framing Error */
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