Annotation of sys/arch/jornada/jornada/jornada720_start.S, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: armish_start.S,v 1.2 2006/05/29 17:30:26 drahn Exp $ */
2: /* $NetBSD: iq80321_start.S,v 1.4 2002/10/14 22:32:54 bjh21 Exp $ */
3:
4: /*
5: * Copyright (c) 2002 Wasabi Systems, Inc.
6: * All rights reserved.
7: *
8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed for the NetBSD Project by
21: * Wasabi Systems, Inc.
22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23: * or promote products derived from this software without specific prior
24: * written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: #include <machine/asm.h>
40: #include <arm/armreg.h>
41: #include <arm/pte.h>
42:
43: .section .start,"ax",%progbits
44:
45: .global _C_LABEL(jornada720_start)
46: _C_LABEL(jornada720_start):
47: #define notsure
48: #ifdef notsure
49: /* Put the processer in SVC mode */
50: mov r5, sp
51: mrs r4, cpsr_all
52: bic r4, r4, #31
53: orr r4, r4, #(PSR_SVC32_MODE)
54: msr cpsr_all, r4
55: mov sp, r5
56:
57: /* Disable PID virtual address mapping */
58: mov r4, #0
59: mcr 15, 0, r4, c13, c0, 0
60: #endif
61: #undef notsure
62: /*
63: * We will go ahead and disable the MMU here so that we don't
64: * have to worry about flushing caches, etc.
65: *
66: * Note that we may not currently be running VA==PA, which means
67: * we'll need to leap to the next insn after disabing the MMU.
68: */
69: adr r8, Lunmapped
70: bic r8, r8, #0xff000000 /* clear upper 8 bits */
71: orr r8, r8, #0xc0000000 /* OR in physical base address */
72:
73:
74: mrc p15, 0, r2, c1, c0, 0
75: bic r2, r2, #CPU_CONTROL_MMU_ENABLE
76: mcr p15, 0, r2, c1, c0, 0
77:
78: nop
79: nop
80: nop
81:
82: mov pc, r8 /* Heave-ho! */
83:
84: Lunmapped:
85: /*
86: * We want to construct a memory map that maps us
87: * VA==PA (SDRAM at 0xc0000000) and also double-maps
88: * that space at 0xc0000000 (where the kernel address
89: * space starts). We create these mappings uncached
90: * and unbuffered to be safe.
91: *
92: * We also want to map the various devices we want to
93: * talk to VA==PA during bootstrap.
94: *
95: * We just use section mappings for all of this to make it easy.
96: *
97: * We will put the L1 table to do all this at 0xc0004000.
98: */
99:
100: /*
101: * Step 1: Map the entire address space VA==PA.
102: */
103: adr r0, Ltable
104: ldr r0, [r0] /* r0 = &l1table */
105:
106: mov r3, #(L1_S_AP(AP_KRW))
107: orr r3, r3, #(L1_TYPE_S)
108: mov r2, #0x100000 /* advance by 1MB */
109: mov r1, #0x1000 /* 4096MB */
110: 1:
111: str r3, [r0], #0x04
112: add r3, r3, r2
113: subs r1, r1, #1
114: bgt 1b
115:
116:
117: /*
118: * Step 2: Map VA 0xc0000000->0xc1ffffff to PA 0xc0000000->0xc1ffffff.
119: */
120: adr r0, Ltable /* r0 = &l1table */
121: ldr r0, [r0]
122:
123: mov r3, #(L1_S_AP(AP_KRW))
124: orr r3, r3, #(L1_TYPE_S)
125: orr r3, r3, #0xc0000000
126: add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */
127: mov r1, #0x20 /* 32MB */
128: 1:
129: str r3, [r0], #0x04
130: add r3, r3, r2
131: subs r1, r1, #1
132: bgt 1b
133:
134: /* OK! Page table is set up. Give it to the CPU. */
135: adr r0, Ltable
136: ldr r0, [r0]
137: mcr p15, 0, r0, c2, c0, 0
138:
139: /* Flush the old TLBs, just in case. */
140: mcr p15, 0, r0, c8, c7, 0
141:
142: /* Set the Domain Access register. Very important! */
143: mov r0, #1
144: mcr p15, 0, r0, c3, c0, 0
145:
146: /* Get ready to jump to the "real" kernel entry point... */
147: ldr r0, Lstart
148:
149: /* OK, let's enable the MMU. */
150: mrc p15, 0, r2, c1, c0, 0
151: orr r2, r2, #CPU_CONTROL_MMU_ENABLE
152: mcr p15, 0, r2, c1, c0, 0
153:
154: nop
155: nop
156: nop
157:
158: /* CPWAIT sequence to make sure the MMU is on... */
159: mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
160: mov r2, r2 /* force it to complete */
161: mov pc, r0 /* leap to kernel entry point! */
162:
163: Ltable:
164: .word 0xc0004000
165:
166: Lstart:
167: .word start
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