File: [local] / sys / arch / jornada / jornada / jornada720_start.S.test (download)
Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:09:00 2008 UTC (16 years, 6 months ago) by nbrk
Branch: OPENBSD_4_2_BASE, MAIN
CVS Tags: jornada-partial-support-wip, HEAD Changes since 1.1: +0 -0 lines
Import of OpenBSD 4.2 release kernel tree with initial code to support
Jornada 720/728, StrongARM 1110-based handheld PC.
At this point kernel roots on NFS and boots into vfs_mountroot() and traps.
What is supported:
- glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode
(needs some palette tweaks for non black/white/blue colors, i think)
- saic, SA11x0 interrupt controller (needs cleanup)
- sacom, SA11x0 UART (supported only as boot console for now)
- SA11x0 GPIO controller fully supported (but can't handle multiple interrupt
handlers on one gpio pin)
- sassp, SSP port on SA11x0 that attaches spibus
- Jornada microcontroller (jmcu) to control kbd, battery, etc throught
the SPI bus (wskbd attaches on jmcu, but not tested)
- tod functions seem work
- initial code for SA-1111 (chip companion) : this is TODO
Next important steps, i think:
- gpio and intc on sa1111
- pcmcia support for sa11x0 (and sa1111 help logic)
- REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs)
- root on wd0! (using already supported PCMCIA-ATA)
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/* $OpenBSD: armish_start.S,v 1.2 2006/05/29 17:30:26 drahn Exp $ */
/* $NetBSD: iq80321_start.S,v 1.4 2002/10/14 22:32:54 bjh21 Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include <arm/armreg.h>
#include <arm/pte.h>
.section .start,"ax",%progbits
.global _C_LABEL(jornada720_start)
_C_LABEL(jornada720_start):
#define notsure
#ifdef notsure
/* Put the processer in SVC mode */
mov r5, sp
mrs r4, cpsr_all
bic r4, r4, #31
orr r4, r4, #(PSR_SVC32_MODE)
msr cpsr_all, r4
mov sp, r5
/* Disable PID virtual address mapping */
mov r4, #0
mcr 15, 0, r4, c13, c0, 0
#endif
#undef notsure
/*
* We will go ahead and disable the MMU here so that we don't
* have to worry about flushing caches, etc.
*
* Note that we may not currently be running VA==PA, which means
* we'll need to leap to the next insn after disabing the MMU.
*/
adr r8, Lunmapped
// bic r8, r8, #0xff000000 /* clear upper 8 bits */
// orr r8, r8, #0xc0000000 /* OR in physical base address */
#if 0
mrc p15, 0, r2, c1, c0, 0
bic r2, r2, #CPU_CONTROL_MMU_ENABLE
mcr p15, 0, r2, c1, c0, 0
#endif
nop
nop
nop
mov pc, r8 /* Heave-ho! */
Lunmapped:
/*
* We want to construct a memory map that maps us
* VA==PA (SDRAM at 0xc0000000) and also double-maps
* that space at 0xc0000000 (where the kernel address
* space starts). We create these mappings uncached
* and unbuffered to be safe.
*
* We also want to map the various devices we want to
* talk to VA==PA during bootstrap.
*
* We just use section mappings for all of this to make it easy.
*
* We will put the L1 table to do all this at 0xc0004000.
*/
adr r0, Lstart
mov pc, r0
#if 0
/*
* Step 1: Map the entire address space VA==PA.
*/
adr r0, Ltable
ldr r0, [r0] /* r0 = &l1table */
mov r3, #(L1_S_AP(AP_KRW))
orr r3, r3, #(L1_TYPE_S)
mov r2, #0x100000 /* advance by 1MB */
mov r1, #0x1000 /* 4096MB */
1:
str r3, [r0], #0x04
add r3, r3, r2
subs r1, r1, #1
bgt 1b
/*
* Step 2: Map VA 0xc0000000->0xc1ffffff to PA 0xc0000000->0xc1ffffff.
*/
adr r0, Ltable /* r0 = &l1table */
ldr r0, [r0]
mov r3, #(L1_S_AP(AP_KRW))
orr r3, r3, #(L1_TYPE_S)
orr r3, r3, #0xc0000000
add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */
mov r1, #0x20 /* 32MB */
1:
str r3, [r0], #0x04
add r3, r3, r2
subs r1, r1, #1
bgt 1b
/* OK! Page table is set up. Give it to the CPU. */
adr r0, Ltable
ldr r0, [r0]
mcr p15, 0, r0, c2, c0, 0
/* Flush the old TLBs, just in case. */
mcr p15, 0, r0, c8, c7, 0
/* Set the Domain Access register. Very important! */
mov r0, #1
mcr p15, 0, r0, c3, c0, 0
/* Get ready to jump to the "real" kernel entry point... */
ldr r0, Lstart
/* OK, let's enable the MMU. */
mrc p15, 0, r2, c1, c0, 0
orr r2, r2, #CPU_CONTROL_MMU_ENABLE
mcr p15, 0, r2, c1, c0, 0
nop
nop
nop
/* CPWAIT sequence to make sure the MMU is on... */
mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
mov r2, r2 /* force it to complete */
mov pc, r0 /* leap to kernel entry point! */
Ltable:
.word 0xc0004000
#endif /* 0 */
Lstart:
.word start