Annotation of sys/arch/jornada/jornada/jornada720_start.S.test, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: armish_start.S,v 1.2 2006/05/29 17:30:26 drahn Exp $ */
! 2: /* $NetBSD: iq80321_start.S,v 1.4 2002/10/14 22:32:54 bjh21 Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 2002 Wasabi Systems, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
! 9: *
! 10: * Redistribution and use in source and binary forms, with or without
! 11: * modification, are permitted provided that the following conditions
! 12: * are met:
! 13: * 1. Redistributions of source code must retain the above copyright
! 14: * notice, this list of conditions and the following disclaimer.
! 15: * 2. Redistributions in binary form must reproduce the above copyright
! 16: * notice, this list of conditions and the following disclaimer in the
! 17: * documentation and/or other materials provided with the distribution.
! 18: * 3. All advertising materials mentioning features or use of this software
! 19: * must display the following acknowledgement:
! 20: * This product includes software developed for the NetBSD Project by
! 21: * Wasabi Systems, Inc.
! 22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
! 23: * or promote products derived from this software without specific prior
! 24: * written permission.
! 25: *
! 26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
! 27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
! 30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 36: * POSSIBILITY OF SUCH DAMAGE.
! 37: */
! 38:
! 39: #include <machine/asm.h>
! 40: #include <arm/armreg.h>
! 41: #include <arm/pte.h>
! 42:
! 43: .section .start,"ax",%progbits
! 44:
! 45: .global _C_LABEL(jornada720_start)
! 46: _C_LABEL(jornada720_start):
! 47: #define notsure
! 48: #ifdef notsure
! 49: /* Put the processer in SVC mode */
! 50: mov r5, sp
! 51: mrs r4, cpsr_all
! 52: bic r4, r4, #31
! 53: orr r4, r4, #(PSR_SVC32_MODE)
! 54: msr cpsr_all, r4
! 55: mov sp, r5
! 56:
! 57: /* Disable PID virtual address mapping */
! 58: mov r4, #0
! 59: mcr 15, 0, r4, c13, c0, 0
! 60: #endif
! 61: #undef notsure
! 62: /*
! 63: * We will go ahead and disable the MMU here so that we don't
! 64: * have to worry about flushing caches, etc.
! 65: *
! 66: * Note that we may not currently be running VA==PA, which means
! 67: * we'll need to leap to the next insn after disabing the MMU.
! 68: */
! 69: adr r8, Lunmapped
! 70: // bic r8, r8, #0xff000000 /* clear upper 8 bits */
! 71: // orr r8, r8, #0xc0000000 /* OR in physical base address */
! 72:
! 73:
! 74: #if 0
! 75: mrc p15, 0, r2, c1, c0, 0
! 76: bic r2, r2, #CPU_CONTROL_MMU_ENABLE
! 77: mcr p15, 0, r2, c1, c0, 0
! 78: #endif
! 79: nop
! 80: nop
! 81: nop
! 82:
! 83: mov pc, r8 /* Heave-ho! */
! 84:
! 85: Lunmapped:
! 86: /*
! 87: * We want to construct a memory map that maps us
! 88: * VA==PA (SDRAM at 0xc0000000) and also double-maps
! 89: * that space at 0xc0000000 (where the kernel address
! 90: * space starts). We create these mappings uncached
! 91: * and unbuffered to be safe.
! 92: *
! 93: * We also want to map the various devices we want to
! 94: * talk to VA==PA during bootstrap.
! 95: *
! 96: * We just use section mappings for all of this to make it easy.
! 97: *
! 98: * We will put the L1 table to do all this at 0xc0004000.
! 99: */
! 100: adr r0, Lstart
! 101: mov pc, r0
! 102: #if 0
! 103: /*
! 104: * Step 1: Map the entire address space VA==PA.
! 105: */
! 106: adr r0, Ltable
! 107: ldr r0, [r0] /* r0 = &l1table */
! 108:
! 109: mov r3, #(L1_S_AP(AP_KRW))
! 110: orr r3, r3, #(L1_TYPE_S)
! 111: mov r2, #0x100000 /* advance by 1MB */
! 112: mov r1, #0x1000 /* 4096MB */
! 113: 1:
! 114: str r3, [r0], #0x04
! 115: add r3, r3, r2
! 116: subs r1, r1, #1
! 117: bgt 1b
! 118:
! 119:
! 120: /*
! 121: * Step 2: Map VA 0xc0000000->0xc1ffffff to PA 0xc0000000->0xc1ffffff.
! 122: */
! 123: adr r0, Ltable /* r0 = &l1table */
! 124: ldr r0, [r0]
! 125:
! 126: mov r3, #(L1_S_AP(AP_KRW))
! 127: orr r3, r3, #(L1_TYPE_S)
! 128: orr r3, r3, #0xc0000000
! 129: add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */
! 130: mov r1, #0x20 /* 32MB */
! 131: 1:
! 132: str r3, [r0], #0x04
! 133: add r3, r3, r2
! 134: subs r1, r1, #1
! 135: bgt 1b
! 136:
! 137: /* OK! Page table is set up. Give it to the CPU. */
! 138: adr r0, Ltable
! 139: ldr r0, [r0]
! 140: mcr p15, 0, r0, c2, c0, 0
! 141:
! 142: /* Flush the old TLBs, just in case. */
! 143: mcr p15, 0, r0, c8, c7, 0
! 144:
! 145: /* Set the Domain Access register. Very important! */
! 146: mov r0, #1
! 147: mcr p15, 0, r0, c3, c0, 0
! 148:
! 149: /* Get ready to jump to the "real" kernel entry point... */
! 150: ldr r0, Lstart
! 151:
! 152: /* OK, let's enable the MMU. */
! 153: mrc p15, 0, r2, c1, c0, 0
! 154: orr r2, r2, #CPU_CONTROL_MMU_ENABLE
! 155: mcr p15, 0, r2, c1, c0, 0
! 156:
! 157: nop
! 158: nop
! 159: nop
! 160:
! 161: /* CPWAIT sequence to make sure the MMU is on... */
! 162: mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
! 163: mov r2, r2 /* force it to complete */
! 164: mov pc, r0 /* leap to kernel entry point! */
! 165:
! 166: Ltable:
! 167: .word 0xc0004000
! 168: #endif /* 0 */
! 169: Lstart:
! 170: .word start
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