Annotation of sys/arch/i386/pci/piixreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: piixreg.h,v 1.4 2003/03/28 23:12:33 mickey Exp $ */
2: /* $NetBSD: piixreg.h,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 1999, by UCHIYAMA Yasushi
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. The name of the developer may NOT be used to endorse or promote products
14: * derived from this software without specific prior written permission.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26: * SUCH DAMAGE.
27: */
28:
29: /*
30: * Register definitions for the Intel PIIX PCI-ISA bridge interrupt controller.
31: */
32:
33: /*
34: * PIRQ[3:0]# - PIRQ ROUTE CONTROL REGISTERS
35: *
36: * PCI Configuration registers 0x60-0x63, 0x68-0x6b
37: */
38:
39: #define PIIX_LEGAL_LINK(link) ((link) >= 0 && (link) <= 7)
40:
41: #define PIIX_PIRQ_MASK 0xdef8
42: #define PIIX_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
43: ((1 << (irq)) & PIIX_PIRQ_MASK) != 0)
44:
45: #define PIIX_CFG_PIRQ 0x60 /* PCI configuration space */
46: #define PIIX_CFG_PIRQH 0x68
47: #define PIIX_CFG_PIRQ_NONE 0x80
48: #define PIIX_CFG_PIRQ_MASK 0x0f
49: #define PIIX_PIRQ(reg, x) (((reg) >> ((x) << 3)) & 0xff)
50:
51: /*
52: * ELCR - EDGE/LEVEL CONTROL REGISTER
53: *
54: * PCI I/O registers 0x4d0, 0x4d1
55: */
56: #define PIIX_REG_ELCR 0x4d0
57: #define PIIX_REG_ELCR_SIZE 2
CVSweb